mirror of https://github.com/acidanthera/audk.git
161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/** @file
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IA32 register defintions needed by debug transfer protocol.
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Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _ARCH_REGISTERS_H_
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#define _ARCH_REGISTERS_H_
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#pragma pack(1)
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///
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/// FXSAVE_STATE
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/// FP / MMX / XMM registers (see fxrstor instruction definition)
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///
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typedef struct {
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UINT16 Fcw;
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UINT16 Fsw;
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UINT16 Ftw;
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UINT16 Opcode;
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UINT32 Eip;
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UINT16 Cs;
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UINT16 Reserved1;
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UINT32 DataOffset;
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UINT16 Ds;
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UINT8 Reserved2[2];
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UINT32 Mxcsr;
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UINT32 Mxcsr_Mask;
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UINT8 St0Mm0[10];
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UINT8 Reserved3[6];
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UINT8 St1Mm1[10];
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UINT8 Reserved4[6];
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UINT8 St2Mm2[10];
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UINT8 Reserved5[6];
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UINT8 St3Mm3[10];
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UINT8 Reserved6[6];
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UINT8 St4Mm4[10];
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UINT8 Reserved7[6];
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UINT8 St5Mm5[10];
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UINT8 Reserved8[6];
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UINT8 St6Mm6[10];
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UINT8 Reserved9[6];
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UINT8 St7Mm7[10];
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UINT8 Reserved10[6];
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UINT8 Xmm0[16];
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UINT8 Xmm1[16];
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UINT8 Xmm2[16];
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UINT8 Xmm3[16];
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UINT8 Xmm4[16];
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UINT8 Xmm5[16];
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UINT8 Xmm6[16];
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UINT8 Xmm7[16];
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UINT8 Reserved11[14 * 16];
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} DEBUG_DATA_IA32_FX_SAVE_STATE;
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///
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/// IA-32 processor context definition
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///
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typedef struct {
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DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
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UINT32 Dr0;
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UINT32 Dr1;
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UINT32 Dr2;
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UINT32 Dr3;
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UINT32 Dr6;
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UINT32 Dr7;
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UINT32 Eflags;
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UINT32 Ldtr;
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UINT32 Tr;
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UINT32 Gdtr[2];
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UINT32 Idtr[2];
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UINT32 Eip;
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UINT32 Gs;
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UINT32 Fs;
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UINT32 Es;
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UINT32 Ds;
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UINT32 Cs;
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UINT32 Ss;
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UINT32 Cr0;
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UINT32 Cr1; ///< Reserved
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UINT32 Cr2;
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UINT32 Cr3;
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UINT32 Cr4;
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UINT32 Edi;
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UINT32 Esi;
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UINT32 Ebp;
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UINT32 Esp;
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UINT32 Edx;
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UINT32 Ecx;
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UINT32 Ebx;
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UINT32 Eax;
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} DEBUG_DATA_IA32_SYSTEM_CONTEXT;
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///
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/// IA32 GROUP register
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///
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typedef struct {
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UINT16 Cs;
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UINT16 Ds;
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UINT16 Es;
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UINT16 Fs;
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UINT16 Gs;
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UINT16 Ss;
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UINT32 Eflags;
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UINT32 Ebp;
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UINT32 Eip;
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UINT32 Esp;
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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UINT32 Edx;
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UINT32 Esi;
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UINT32 Edi;
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UINT32 Dr0;
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UINT32 Dr1;
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UINT32 Dr2;
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UINT32 Dr3;
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UINT32 Dr6;
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UINT32 Dr7;
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} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;
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///
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/// IA32 Segment Limit GROUP register
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///
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typedef struct {
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UINT32 CsLim;
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UINT32 SsLim;
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UINT32 GsLim;
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UINT32 FsLim;
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UINT32 EsLim;
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UINT32 DsLim;
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UINT32 LdtLim;
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UINT32 TssLim;
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} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;
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///
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/// IA32 Segment Base GROUP register
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///
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typedef struct {
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UINT32 CsBas;
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UINT32 SsBas;
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UINT32 GsBas;
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UINT32 FsBas;
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UINT32 EsBas;
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UINT32 DsBas;
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UINT32 LdtBas;
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UINT32 TssBas;
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} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;
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#pragma pack()
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#endif
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