mirror of https://github.com/acidanthera/audk.git
403 lines
10 KiB
C
403 lines
10 KiB
C
/** @file
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Handle OMAP35xx interrupt controller
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmLib.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/HardwareInterrupt.h>
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#include <Omap3530/Omap3530.h>
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//
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// Notifications
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//
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EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
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HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];
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/**
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Shutdown our hardware
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DXE Core will disable interrupts and turn off the timer and disable interrupts
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after all the event handlers have run.
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@param[in] Event The Event that is being processed
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@param[in] Context Event Context
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**/
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VOID
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EFIAPI
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ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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// Disable all interrupts
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MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
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MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
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MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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// Add code here to disable all FIQs as debugger may have turned one on
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}
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/**
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Register Handler for the specified interrupt source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param Handler Callback for interrupt. NULL to unregister
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@retval EFI_SUCCESS Source was updated to support Handler.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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RegisterInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN HARDWARE_INTERRUPT_HANDLER Handler
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)
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{
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if (Source > MAX_VECTOR) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {
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// This vector has been programmed as FIQ so we can't use it for IRQ
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// EFI does not use FIQ, but the debugger can use it to check for
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// ctrl-c. So this ASSERT means you have a conflict with the debug agent
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
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return EFI_ALREADY_STARTED;
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}
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gRegisteredInterruptHandlers[Source] = Handler;
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return This->EnableInterruptSource(This, Source);
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}
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/**
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Enable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt enabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINTN Bank;
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UINTN Bit;
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if (Source > MAX_VECTOR) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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Bank = Source / 32;
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Bit = 1UL << (Source % 32);
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MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
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return EFI_SUCCESS;
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}
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/**
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Disable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt disabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINTN Bank;
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UINTN Bit;
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if (Source > MAX_VECTOR) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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Bank = Source / 32;
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Bit = 1UL << (Source % 32);
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MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
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return EFI_SUCCESS;
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}
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/**
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Return current state of interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param InterruptState TRUE: source enabled, FALSE: source disabled.
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@retval EFI_SUCCESS InterruptState is valid
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@retval EFI_DEVICE_ERROR InterruptState is not valid
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**/
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EFI_STATUS
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EFIAPI
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GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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)
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{
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UINTN Bank;
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UINTN Bit;
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if (InterruptState == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if (Source > MAX_VECTOR) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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Bank = Source / 32;
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Bit = 1UL << (Source % 32);
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if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
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*InterruptState = FALSE;
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} else {
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*InterruptState = TRUE;
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}
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return EFI_SUCCESS;
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}
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/**
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Signal to the hardware that the End Of Intrrupt state
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has been reached.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt EOI'ed.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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ArmDataSynchronizationBarrier ();
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return EFI_SUCCESS;
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}
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/**
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EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
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@param InterruptType Defines the type of interrupt or exception that
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occurred on the processor.This parameter is processor architecture specific.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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@return None
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**/
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VOID
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EFIAPI
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IrqInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINT32 Vector;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
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// Needed to prevent infinite nesting when Time Driver lowers TPL
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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ArmDataSynchronizationBarrier ();
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InterruptHandler = gRegisteredInterruptHandlers[Vector];
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if (InterruptHandler != NULL) {
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// Call the registered interrupt handler.
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InterruptHandler (Vector, SystemContext);
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}
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// Needed to clear after running the handler
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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ArmDataSynchronizationBarrier ();
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}
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//
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// Making this global saves a few bytes in image size
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//
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EFI_HANDLE gHardwareInterruptHandle = NULL;
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//
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// The protocol instance produced by this driver
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//
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
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RegisterInterruptSource,
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EnableInterruptSource,
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DisableInterruptSource,
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GetInterruptSourceState,
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EndOfInterrupt
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};
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STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
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STATIC
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VOID
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EFIAPI
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CpuArchEventProtocolNotify (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_CPU_ARCH_PROTOCOL *Cpu;
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EFI_STATUS Status;
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//
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// Get the CPU protocol that this driver requires.
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//
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Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: gBS->LocateProtocol() - %r\n", __FUNCTION__,
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Status));
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ASSERT (FALSE);
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return;
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}
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//
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// Unregister the default exception handler.
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//
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Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, NULL);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
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__FUNCTION__, Status));
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ASSERT (FALSE);
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return;
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}
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//
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// Register to receive interrupts
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//
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Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ,
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IrqInterruptHandler);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
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__FUNCTION__, Status));
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ASSERT (FALSE);
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return;
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}
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}
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/**
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Initialize the state information for the CPU Architectural Protocol
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@param ImageHandle of the loaded driver
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@param SystemTable Pointer to the System Table
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@retval EFI_SUCCESS Protocol registered
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Hardware problems
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**/
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EFI_STATUS
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InterruptDxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT CpuArchEvent;
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// Make sure the Interrupt Controller Protocol is not already installed in the system.
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ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
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// Make sure all interrupts are disabled by default.
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MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
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MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
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MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
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MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
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&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
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NULL);
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ASSERT_EFI_ERROR(Status);
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//
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// Install the interrupt handler as soon as the CPU arch protocol appears.
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//
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CpuArchEvent = EfiCreateProtocolNotifyEvent (
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&gEfiCpuArchProtocolGuid,
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TPL_CALLBACK,
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CpuArchEventProtocolNotify,
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NULL,
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&mCpuArchProtocolNotifyEventRegistration
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);
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ASSERT (CpuArchEvent != NULL);
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// Register for an ExitBootServicesEvent
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Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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gBS->CloseEvent (CpuArchEvent);
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}
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return Status;
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}
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