mirror of https://github.com/acidanthera/audk.git
816 lines
24 KiB
C
816 lines
24 KiB
C
/** @file
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Header file for Registers and Structure definitions
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Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OPAL_PASSWORD_NVME_REG_H__
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#define __OPAL_PASSWORD_NVME_REG_H__
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//
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// PCI Header for PCIe root port configuration
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//
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#define NVME_PCIE_PCICMD 0x04
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#define NVME_PCIE_BNUM 0x18
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#define NVME_PCIE_SEC_BNUM 0x19
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#define NVME_PCIE_IOBL 0x1C
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#define NVME_PCIE_MBL 0x20
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#define NVME_PCIE_PMBL 0x24
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#define NVME_PCIE_PMBU32 0x28
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#define NVME_PCIE_PMLU32 0x2C
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#define NVME_PCIE_INTR 0x3C
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//
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// NVMe related definitions
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//
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#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
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#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
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#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
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#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
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#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
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#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
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#define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
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#define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)
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#define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)
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#define NVME_PRP_SIZE (4) // Pages of PRP list
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#define NVME_CONTROLLER_ID 0
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//
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// Time out Value for Nvme transaction execution
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//
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#define NVME_GENERIC_TIMEOUT 5000000 ///< us
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#define NVME_CMD_WAIT 100 ///< us
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#define NVME_CMD_TIMEOUT 20000000 ///< us
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#define NVME_MEM_MAX_SIZE \
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(( \
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1 /* Controller Data */ + \
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1 /* Identify Data */ + \
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1 /* ASQ */ + \
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1 /* ACQ */ + \
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1 /* SQs */ + \
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1 /* CQs */ + \
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NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ + \
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1 /* SECURITY */ \
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) * EFI_PAGE_SIZE)
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//
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// controller register offsets
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//
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#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
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#define NVME_VER_OFFSET 0x0008 // Version
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#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
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#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
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#define NVME_CC_OFFSET 0x0014 // Controller Configuration
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#define NVME_CSTS_OFFSET 0x001c // Controller Status
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#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
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#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
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#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
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#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
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#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
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//
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// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
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// Get the doorbell stride bit shift Value from the controller capabilities.
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//
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#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
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#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
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#pragma pack(1)
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//
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// 3.1.1 Offset 00h: CAP - Controller Capabilities
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//
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typedef struct {
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UINT16 Mqes; // Maximum Queue Entries Supported
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UINT8 Cqr:1; // Contiguous Queues Required
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UINT8 Ams:2; // Arbitration Mechanism Supported
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UINT8 Rsvd1:5;
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UINT8 To; // Timeout
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UINT16 Dstrd:4;
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UINT16 Rsvd2:1;
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UINT16 Css:4; // Command Sets Supported
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UINT16 Rsvd3:7;
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UINT8 Mpsmin:4;
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UINT8 Mpsmax:4;
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UINT8 Rsvd4;
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} NVME_CAP;
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//
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// 3.1.2 Offset 08h: VS - Version
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//
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typedef struct {
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UINT16 Mnr; // Minor version number
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UINT16 Mjr; // Major version number
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} NVME_VER;
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//
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// 3.1.5 Offset 14h: CC - Controller Configuration
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//
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typedef struct {
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UINT16 En:1; // Enable
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UINT16 Rsvd1:3;
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UINT16 Css:3; // Command Set Selected
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UINT16 Mps:4; // Memory Page Size
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UINT16 Ams:3; // Arbitration Mechanism Selected
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UINT16 Shn:2; // Shutdown Notification
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UINT8 Iosqes:4; // I/O Submission Queue Entry Size
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UINT8 Iocqes:4; // I/O Completion Queue Entry Size
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UINT8 Rsvd2;
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} NVME_CC;
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//
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// 3.1.6 Offset 1Ch: CSTS - Controller Status
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//
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typedef struct {
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UINT32 Rdy:1; // Ready
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UINT32 Cfs:1; // Controller Fatal Status
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UINT32 Shst:2; // Shutdown Status
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UINT32 Nssro:1; // NVM Subsystem Reset Occurred
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UINT32 Rsvd1:27;
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} NVME_CSTS;
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//
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// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
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//
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typedef struct {
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UINT16 Asqs:12; // Submission Queue Size
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UINT16 Rsvd1:4;
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UINT16 Acqs:12; // Completion Queue Size
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UINT16 Rsvd2:4;
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} NVME_AQA;
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//
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// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
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//
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#define NVME_ASQ UINT64
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//
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// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
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//
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#define NVME_ACQ UINT64
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//
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// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
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//
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typedef struct {
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UINT16 Sqt;
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UINT16 Rsvd1;
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} NVME_SQTDBL;
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//
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// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
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//
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typedef struct {
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UINT16 Cqh;
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UINT16 Rsvd1;
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} NVME_CQHDBL;
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//
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// NVM command set structures
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//
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// Read Command
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//
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typedef struct {
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//
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// CDW 10, 11
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//
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UINT64 Slba; /* Starting Sector Address */
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//
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// CDW 12
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//
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UINT16 Nlb; /* Number of Sectors */
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UINT16 Rsvd1:10;
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UINT16 Prinfo:4; /* Protection Info Check */
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UINT16 Fua:1; /* Force Unit Access */
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UINT16 Lr:1; /* Limited Retry */
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//
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// CDW 13
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//
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UINT32 Af:4; /* Access Frequency */
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UINT32 Al:2; /* Access Latency */
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UINT32 Sr:1; /* Sequential Request */
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UINT32 In:1; /* Incompressible */
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UINT32 Rsvd2:24;
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//
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// CDW 14
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//
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UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
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//
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// CDW 15
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//
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UINT16 Elbat; /* Expected Logical Block Application Tag */
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UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
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} NVME_READ;
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//
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// Write Command
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//
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typedef struct {
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//
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// CDW 10, 11
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//
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UINT64 Slba; /* Starting Sector Address */
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//
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// CDW 12
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//
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UINT16 Nlb; /* Number of Sectors */
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UINT16 Rsvd1:10;
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UINT16 Prinfo:4; /* Protection Info Check */
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UINT16 Fua:1; /* Force Unit Access */
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UINT16 Lr:1; /* Limited Retry */
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//
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// CDW 13
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//
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UINT32 Af:4; /* Access Frequency */
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UINT32 Al:2; /* Access Latency */
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UINT32 Sr:1; /* Sequential Request */
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UINT32 In:1; /* Incompressible */
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UINT32 Rsvd2:24;
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//
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// CDW 14
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//
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UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
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//
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// CDW 15
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//
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UINT16 Lbat; /* Logical Block Application Tag */
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UINT16 Lbatm; /* Logical Block Application Tag Mask */
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} NVME_WRITE;
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//
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// Flush
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//
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typedef struct {
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//
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// CDW 10
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//
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UINT32 Flush; /* Flush */
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} NVME_FLUSH;
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//
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// Write Uncorrectable command
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//
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typedef struct {
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//
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// CDW 10, 11
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//
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UINT64 Slba; /* Starting LBA */
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//
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// CDW 12
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//
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UINT32 Nlb:16; /* Number of Logical Blocks */
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UINT32 Rsvd1:16;
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} NVME_WRITE_UNCORRECTABLE;
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//
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// Write Zeroes command
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//
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typedef struct {
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//
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// CDW 10, 11
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//
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UINT64 Slba; /* Starting LBA */
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//
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// CDW 12
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//
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UINT16 Nlb; /* Number of Logical Blocks */
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UINT16 Rsvd1:10;
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UINT16 Prinfo:4; /* Protection Info Check */
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UINT16 Fua:1; /* Force Unit Access */
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UINT16 Lr:1; /* Limited Retry */
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//
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// CDW 13
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//
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UINT32 Rsvd2;
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//
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// CDW 14
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//
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UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
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//
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// CDW 15
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//
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UINT16 Lbat; /* Logical Block Application Tag */
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UINT16 Lbatm; /* Logical Block Application Tag Mask */
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} NVME_WRITE_ZEROES;
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//
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// Compare command
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//
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typedef struct {
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//
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// CDW 10, 11
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//
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UINT64 Slba; /* Starting LBA */
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//
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// CDW 12
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//
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UINT16 Nlb; /* Number of Logical Blocks */
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UINT16 Rsvd1:10;
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UINT16 Prinfo:4; /* Protection Info Check */
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UINT16 Fua:1; /* Force Unit Access */
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UINT16 Lr:1; /* Limited Retry */
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//
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// CDW 13
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//
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UINT32 Rsvd2;
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//
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// CDW 14
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//
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UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
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//
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// CDW 15
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//
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UINT16 Elbat; /* Expected Logical Block Application Tag */
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UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
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} NVME_COMPARE;
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typedef union {
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NVME_READ Read;
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NVME_WRITE Write;
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NVME_FLUSH Flush;
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NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
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NVME_WRITE_ZEROES WriteZeros;
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NVME_COMPARE Compare;
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} NVME_CMD;
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typedef struct {
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UINT16 Mp; /* Maximum Power */
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UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 Mps:1; /* Max Power Scale */
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UINT8 Nops:1; /* Non-Operational State */
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UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
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UINT32 Enlat; /* Entry Latency */
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UINT32 Exlat; /* Exit Latency */
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UINT8 Rrt:5; /* Relative Read Throughput */
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UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 Rrl:5; /* Relative Read Leatency */
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UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 Rwt:5; /* Relative Write Throughput */
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UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 Rwl:5; /* Relative Write Leatency */
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UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
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} NVME_PSDESCRIPTOR;
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//
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// Identify Controller Data
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//
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typedef struct {
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//
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// Controller Capabilities and Features 0-255
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//
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UINT16 Vid; /* PCI Vendor ID */
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UINT16 Ssvid; /* PCI sub-system vendor ID */
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UINT8 Sn[20]; /* Produce serial number */
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UINT8 Mn[40]; /* Proeduct model number */
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UINT8 Fr[8]; /* Firmware Revision */
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UINT8 Rab; /* Recommended Arbitration Burst */
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UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */
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UINT8 Cmic; /* Multi-interface Capabilities */
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UINT8 Mdts; /* Maximum Data Transfer Size */
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UINT8 Cntlid[2]; /* Controller ID */
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UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
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//
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// Admin Command Set Attributes
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//
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UINT16 Oacs; /* Optional Admin Command Support */
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UINT8 Acl; /* Abort Command Limit */
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UINT8 Aerl; /* Async Event Request Limit */
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UINT8 Frmw; /* Firmware updates */
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UINT8 Lpa; /* Log Page Attributes */
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UINT8 Elpe; /* Error Log Page Entries */
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UINT8 Npss; /* Number of Power States Support */
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UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
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UINT8 Apsta; /* Autonomous Power State Transition Attributes */
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UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
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//
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// NVM Command Set Attributes
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//
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UINT8 Sqes; /* Submission Queue Entry Size */
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UINT8 Cqes; /* Completion Queue Entry Size */
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UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
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UINT32 Nn; /* Number of Namespaces */
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UINT16 Oncs; /* Optional NVM Command Support */
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UINT16 Fuses; /* Fused Operation Support */
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UINT8 Fna; /* Format NVM Attributes */
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UINT8 Vwc; /* Volatile Write Cache */
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UINT16 Awun; /* Atomic Write Unit Normal */
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UINT16 Awupf; /* Atomic Write Unit Power Fail */
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UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
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UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
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UINT16 Acwu; /* Atomic Compare & Write Unit */
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UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
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UINT32 Sgls; /* SGL Support */
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UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
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//
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// I/O Command set Attributes
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//
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UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
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//
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// Power State Descriptors
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//
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NVME_PSDESCRIPTOR PsDescriptor[32];
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UINT8 VendorData[1024]; /* Vendor specific Data */
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} NVME_ADMIN_CONTROLLER_DATA;
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typedef struct {
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UINT16 Security : 1; /* supports security send/receive commands */
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UINT16 Format : 1; /* supports format nvm command */
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UINT16 Firmware : 1; /* supports firmware activate/download commands */
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UINT16 Oacs_rsvd : 13;
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} OACS; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs
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typedef struct {
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UINT16 Ms; /* Metadata Size */
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UINT8 Lbads; /* LBA Data Size */
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UINT8 Rp:2; /* Relative Performance */
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#define LBAF_RP_BEST 00b
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#define LBAF_RP_BETTER 01b
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#define LBAF_RP_GOOD 10b
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#define LBAF_RP_DEGRADED 11b
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UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
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} NVME_LBAFORMAT;
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//
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// Identify Namespace Data
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//
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typedef struct {
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//
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// NVM Command Set Specific
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//
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UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
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UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
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UINT64 Nuse; /* Namespace Utilization */
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UINT8 Nsfeat; /* Namespace Features */
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UINT8 Nlbaf; /* Number of LBA Formats */
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UINT8 Flbas; /* Formatted LBA Size */
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UINT8 Mc; /* Metadata Capabilities */
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UINT8 Dpc; /* End-to-end Data Protection capabilities */
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UINT8 Dps; /* End-to-end Data Protection Type Settings */
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UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
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UINT8 Rescap; /* Reservation Capabilities */
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UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
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UINT64 Eui64; /* IEEE Extended Unique Identifier */
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//
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// LBA Format
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//
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NVME_LBAFORMAT LbaFormat[16];
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UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
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UINT8 VendorData[3712]; /* Vendor specific Data */
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} NVME_ADMIN_NAMESPACE_DATA;
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//
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// NvmExpress Admin Identify Cmd
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//
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typedef struct {
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//
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// CDW 10
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//
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UINT32 Cns:2;
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UINT32 Rsvd1:30;
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} NVME_ADMIN_IDENTIFY;
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//
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// NvmExpress Admin Create I/O Completion Queue
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//
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typedef struct {
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//
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// CDW 10
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//
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UINT32 Qid:16; /* Queue Identifier */
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UINT32 Qsize:16; /* Queue Size */
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//
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// CDW 11
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//
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UINT32 Pc:1; /* Physically Contiguous */
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UINT32 Ien:1; /* Interrupts Enabled */
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UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
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UINT32 Iv:16; /* Interrupt Vector */
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|
} NVME_ADMIN_CRIOCQ;
|
|
|
|
//
|
|
// NvmExpress Admin Create I/O Submission Queue
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Qid:16; /* Queue Identifier */
|
|
UINT32 Qsize:16; /* Queue Size */
|
|
|
|
//
|
|
// CDW 11
|
|
//
|
|
UINT32 Pc:1; /* Physically Contiguous */
|
|
UINT32 Qprio:2; /* Queue Priority */
|
|
UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
|
|
UINT32 Cqid:16; /* Completion Queue ID */
|
|
} NVME_ADMIN_CRIOSQ;
|
|
|
|
//
|
|
// NvmExpress Admin Delete I/O Completion Queue
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT16 Qid;
|
|
UINT16 Rsvd1;
|
|
} NVME_ADMIN_DEIOCQ;
|
|
|
|
//
|
|
// NvmExpress Admin Delete I/O Submission Queue
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT16 Qid;
|
|
UINT16 Rsvd1;
|
|
} NVME_ADMIN_DEIOSQ;
|
|
|
|
//
|
|
// NvmExpress Admin Security Send
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Resv:8; /* Reserve */
|
|
UINT32 Spsp:16; /* SP Specific */
|
|
UINT32 Secp:8; /* Security Protocol */
|
|
|
|
//
|
|
// CDW 11
|
|
//
|
|
UINT32 Tl; /* Transfer Length */
|
|
} NVME_ADMIN_SECSEND;
|
|
|
|
//
|
|
// NvmExpress Admin Abort Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Sqid:16; /* Submission Queue identifier */
|
|
UINT32 Cid:16; /* Command Identifier */
|
|
} NVME_ADMIN_ABORT;
|
|
|
|
//
|
|
// NvmExpress Admin Firmware Activate Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Fs:3; /* Submission Queue identifier */
|
|
UINT32 Aa:2; /* Command Identifier */
|
|
UINT32 Rsvd1:27;
|
|
} NVME_ADMIN_FIRMWARE_ACTIVATE;
|
|
|
|
//
|
|
// NvmExpress Admin Firmware Image Download Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Numd; /* Number of Dwords */
|
|
//
|
|
// CDW 11
|
|
//
|
|
UINT32 Ofst; /* Offset */
|
|
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
|
|
|
|
//
|
|
// NvmExpress Admin Get Features Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Fid:8; /* Feature Identifier */
|
|
UINT32 Sel:3; /* Select */
|
|
UINT32 Rsvd1:21;
|
|
} NVME_ADMIN_GET_FEATURES;
|
|
|
|
//
|
|
// NvmExpress Admin Get Log Page Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Lid:8; /* Log Page Identifier */
|
|
#define LID_ERROR_INFO
|
|
#define LID_SMART_INFO
|
|
#define LID_FW_SLOT_INFO
|
|
UINT32 Rsvd1:8;
|
|
UINT32 Numd:12; /* Number of Dwords */
|
|
UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
|
|
} NVME_ADMIN_GET_LOG_PAGE;
|
|
|
|
//
|
|
// NvmExpress Admin Set Features Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Fid:8; /* Feature Identifier */
|
|
UINT32 Rsvd1:23;
|
|
UINT32 Sv:1; /* Save */
|
|
} NVME_ADMIN_SET_FEATURES;
|
|
|
|
//
|
|
// NvmExpress Admin Format NVM Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Lbaf:4; /* LBA Format */
|
|
UINT32 Ms:1; /* Metadata Settings */
|
|
UINT32 Pi:3; /* Protection Information */
|
|
UINT32 Pil:1; /* Protection Information Location */
|
|
UINT32 Ses:3; /* Secure Erase Settings */
|
|
UINT32 Rsvd1:20;
|
|
} NVME_ADMIN_FORMAT_NVM;
|
|
|
|
//
|
|
// NvmExpress Admin Security Receive Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Rsvd1:8;
|
|
UINT32 Spsp:16; /* SP Specific */
|
|
UINT32 Secp:8; /* Security Protocol */
|
|
//
|
|
// CDW 11
|
|
//
|
|
UINT32 Al; /* Allocation Length */
|
|
} NVME_ADMIN_SECURITY_RECEIVE;
|
|
|
|
//
|
|
// NvmExpress Admin Security Send Command
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 10
|
|
//
|
|
UINT32 Rsvd1:8;
|
|
UINT32 Spsp:16; /* SP Specific */
|
|
UINT32 Secp:8; /* Security Protocol */
|
|
//
|
|
// CDW 11
|
|
//
|
|
UINT32 Tl; /* Transfer Length */
|
|
} NVME_ADMIN_SECURITY_SEND;
|
|
|
|
typedef union {
|
|
NVME_ADMIN_IDENTIFY Identify;
|
|
NVME_ADMIN_CRIOCQ CrIoCq;
|
|
NVME_ADMIN_CRIOSQ CrIoSq;
|
|
NVME_ADMIN_DEIOCQ DeIoCq;
|
|
NVME_ADMIN_DEIOSQ DeIoSq;
|
|
NVME_ADMIN_ABORT Abort;
|
|
NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
|
|
NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
|
|
NVME_ADMIN_GET_FEATURES GetFeatures;
|
|
NVME_ADMIN_GET_LOG_PAGE GetLogPage;
|
|
NVME_ADMIN_SET_FEATURES SetFeatures;
|
|
NVME_ADMIN_FORMAT_NVM FormatNvm;
|
|
NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
|
|
NVME_ADMIN_SECURITY_SEND SecuritySend;
|
|
} NVME_ADMIN_CMD;
|
|
|
|
typedef struct {
|
|
UINT32 Cdw10;
|
|
UINT32 Cdw11;
|
|
UINT32 Cdw12;
|
|
UINT32 Cdw13;
|
|
UINT32 Cdw14;
|
|
UINT32 Cdw15;
|
|
} NVME_RAW;
|
|
|
|
typedef union {
|
|
NVME_ADMIN_CMD Admin; // Union of Admin commands
|
|
NVME_CMD Nvm; // Union of Nvm commands
|
|
NVME_RAW Raw;
|
|
} NVME_PAYLOAD;
|
|
|
|
//
|
|
// Submission Queue
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 0, Common to all comnmands
|
|
//
|
|
UINT8 Opc; // Opcode
|
|
UINT8 Fuse:2; // Fused Operation
|
|
UINT8 Rsvd1:5;
|
|
UINT8 Psdt:1; // PRP or SGL for Data Transfer
|
|
UINT16 Cid; // Command Identifier
|
|
|
|
//
|
|
// CDW 1
|
|
//
|
|
UINT32 Nsid; // Namespace Identifier
|
|
|
|
//
|
|
// CDW 2,3
|
|
//
|
|
UINT64 Rsvd2;
|
|
|
|
//
|
|
// CDW 4,5
|
|
//
|
|
UINT64 Mptr; // Metadata Pointer
|
|
|
|
//
|
|
// CDW 6-9
|
|
//
|
|
UINT64 Prp[2]; // First and second PRP entries
|
|
|
|
NVME_PAYLOAD Payload;
|
|
|
|
} NVME_SQ;
|
|
|
|
//
|
|
// Completion Queue
|
|
//
|
|
typedef struct {
|
|
//
|
|
// CDW 0
|
|
//
|
|
UINT32 Dword0;
|
|
//
|
|
// CDW 1
|
|
//
|
|
UINT32 Rsvd1;
|
|
//
|
|
// CDW 2
|
|
//
|
|
UINT16 Sqhd; // Submission Queue Head Pointer
|
|
UINT16 Sqid; // Submission Queue Identifier
|
|
//
|
|
// CDW 3
|
|
//
|
|
UINT16 Cid; // Command Identifier
|
|
UINT16 Pt:1; // Phase Tag
|
|
UINT16 Sc:8; // Status Code
|
|
UINT16 Sct:3; // Status Code Type
|
|
UINT16 Rsvd2:2;
|
|
UINT16 Mo:1; // More
|
|
UINT16 Dnr:1; // Retry
|
|
} NVME_CQ;
|
|
|
|
//
|
|
// Nvm Express Admin cmd opcodes
|
|
//
|
|
#define NVME_ADMIN_DELIOSQ_OPC 0
|
|
#define NVME_ADMIN_CRIOSQ_OPC 1
|
|
#define NVME_ADMIN_DELIOCQ_OPC 4
|
|
#define NVME_ADMIN_CRIOCQ_OPC 5
|
|
#define NVME_ADMIN_IDENTIFY_OPC 6
|
|
#define NVME_ADMIN_SECURITY_SEND_OPC 0x81
|
|
#define NVME_ADMIN_SECURITY_RECV_OPC 0x82
|
|
|
|
#define NVME_IO_FLUSH_OPC 0
|
|
#define NVME_IO_WRITE_OPC 1
|
|
#define NVME_IO_READ_OPC 2
|
|
|
|
//
|
|
// Offset from the beginning of private Data queue Buffer
|
|
//
|
|
#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
|
|
|
|
#pragma pack()
|
|
|
|
#endif
|
|
|