mirror of https://github.com/acidanthera/audk.git
415 lines
10 KiB
C
415 lines
10 KiB
C
/**@file
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Platform PEI driver
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Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Ppi/MasterBootMode.h>
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#include <IndustryStandard/Pci22.h>
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#include <OvmfPlatforms.h>
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#include "Platform.h"
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#include "Cmos.h"
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EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
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{ EfiACPIMemoryNVS, 0x004 },
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{ EfiACPIReclaimMemory, 0x008 },
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{ EfiReservedMemoryType, 0x004 },
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{ EfiRuntimeServicesData, 0x024 },
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{ EfiRuntimeServicesCode, 0x030 },
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{ EfiBootServicesCode, 0x180 },
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{ EfiBootServicesData, 0xF00 },
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{ EfiMaxMemoryType, 0x000 }
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};
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EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMasterBootModePpiGuid,
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NULL
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}
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};
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EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
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BOOLEAN mS3Supported = FALSE;
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddUntestedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddUntestedMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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MemMapInitialization (
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VOID
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)
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{
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//
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// Create Memory Type Information HOB
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//
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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mDefaultMemoryTypeInformation,
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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0xC000,
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0x4000
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);
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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if (!mXen) {
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UINT32 TopOfLowRam;
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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//
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// address purpose size
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// ------------ -------- -------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 1023 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
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BASE_2GB : TopOfLowRam, 0xFC000000);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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}
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}
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VOID
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MiscInitialization (
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VOID
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)
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{
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UINT16 HostBridgeDevId;
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UINTN PmCmd;
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UINTN Pmba;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU hob with 36-bit addressing and 16-bits of IO space.
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//
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BuildCpuHob (36, 16);
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//
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// Query Host Bridge DID to determine platform type and save to PCD
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
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AcpiEnBit = BIT0; // PIIX4_PMIOSE
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
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AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL
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AcpiEnBit = BIT7; // Q35_ACPI_EN
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, HostBridgeDevId));
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ASSERT (FALSE);
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return;
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}
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PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);
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//
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// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
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// has been configured (e.g., by Xen) and skip the setup here.
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// This matches the logic in AcpiTimerLibConstructor ().
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// The PEI phase should be exited with fully accessibe ACPI PM IO space:
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// 1. set PMBA
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//
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PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
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//
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// 2. set PCICMD/IOSE
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//
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PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
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//
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// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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}
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VOID
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BootModeInitialization (
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VOID
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)
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{
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EFI_STATUS Status;
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if (CmosRead8 (0xF) == 0xFE) {
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mBootMode = BOOT_ON_S3_RESUME;
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}
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Status = PeiServicesSetBootMode (mBootMode);
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ASSERT_EFI_ERROR (Status);
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Status = PeiServicesInstallPpi (mPpiBootMode);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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ReserveEmuVariableNvStore (
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)
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{
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EFI_PHYSICAL_ADDRESS VariableStore;
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//
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// Allocate storage for NV variables early on so it will be
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// at a consistent address. Since VM memory is preserved
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// across reboots, this allows the NV variable storage to survive
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// a VM reboot.
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//
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VariableStore =
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(EFI_PHYSICAL_ADDRESS)(UINTN)
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AllocateAlignedRuntimePages (
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EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
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PcdGet32 (PcdFlashNvStorageFtwSpareSize)
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);
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DEBUG ((EFI_D_INFO,
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"Reserved variable store memory: 0x%lX; size: %dkb\n",
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VariableStore,
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(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
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));
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PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
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}
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VOID
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DebugDumpCmos (
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VOID
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)
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{
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UINTN Loop;
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DEBUG ((EFI_D_INFO, "CMOS:\n"));
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for (Loop = 0; Loop < 0x80; Loop++) {
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if ((Loop % 0x10) == 0) {
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DEBUG ((EFI_D_INFO, "%02x:", Loop));
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}
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DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
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if ((Loop % 0x10) == 0xf) {
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DEBUG ((EFI_D_INFO, "\n"));
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}
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}
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}
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/**
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Perform Platform PEI initialization.
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@param FileHandle Handle of the file being invoked.
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@param PeiServices Describes the list of possible PEI Services.
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@return EFI_SUCCESS The PEIM initialized successfully.
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**/
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EFI_STATUS
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EFIAPI
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InitializePlatform (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
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DebugDumpCmos ();
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XenDetect ();
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if (QemuFwCfgS3Enabled ()) {
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DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
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mS3Supported = TRUE;
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}
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BootModeInitialization ();
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PublishPeiMemory ();
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InitializeRamRegions ();
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if (mXen) {
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DEBUG ((EFI_D_INFO, "Xen was detected\n"));
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InitializeXen ();
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}
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if (mBootMode != BOOT_ON_S3_RESUME) {
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ReserveEmuVariableNvStore ();
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PeiFvInitialization ();
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MemMapInitialization ();
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}
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MiscInitialization ();
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return EFI_SUCCESS;
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}
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