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audk/OvmfPkg/RiscVVirt
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Tuan Phan f220dcbba8 UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode 
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 		2023-07-15 14:10:18 +00:00
..
Library OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size 2023-07-15 14:10:18 +00:00
PciCpuIo2Dxe OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module 2023-02-16 05:53:28 +00:00
Sec OvmfPkg: RiscVVirt: Remove satp bare mode setting 2023-07-15 14:10:18 +00:00
README.md OvmfPkg/RiscVVirt: Add a readme for build and test 2023-06-23 04:49:11 +00:00
RiscVVirt.dsc.inc UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode 2023-07-15 14:10:18 +00:00
RiscVVirt.fdf.inc OvmfPkg/RiscVVirt: Add support for separate code and variable store 2023-06-23 04:49:11 +00:00
RiscVVirtQemu.dsc OvmfPkg: move PciEncoding into AcpiPlatformLib 2023-06-23 17:26:37 +00:00
RiscVVirtQemu.fdf OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list 2023-07-15 14:10:18 +00:00
VarStore.fdf.inc OvmfPkg/RiscVVirt: Fix couple of issues in VarStore 2023-06-23 04:49:11 +00:00

README.md

Support for RISC-V QEMU virt platform

Overview

RISC-V QEMU 'virt' is a generic platform which does not correspond to any real hardware.

EDK2 for RISC-V virt platform is a payload (S-mode) for the previous stage M-mode firmware like OpenSBI. It follows PEI less design.

The minimum QEMU version required is 8.1 or with commit 7efd65423a which supports separate pflash devices for EDK2 code and variable storage.

Build

export WORKSPACE=`pwd`
export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
export PACKAGES_PATH=$WORKSPACE/edk2
export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
source edk2/edksetup.sh
make -C edk2/BaseTools
source edk2/edksetup.sh BaseTools
build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t GCC5

Test

Below example shows how to boot openSUSE Tumbleweed E20.

  1. RISC-V QEMU pflash devices should be of of size 32MiB.

    truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_CODE.fd

    truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_VARS.fd

  2. Running QEMU

     qemu-system-riscv64 \
 -M virt,pflash0=pflash0,pflash1=pflash1,acpi=off \
 -m 4096 -smp 2 \
 -serial mon:stdio \
 -device virtio-gpu-pci -full-screen \
 -device qemu-xhci \
 -device usb-kbd \
 -device virtio-rng-pci \
 -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
 -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \
 -netdev user,id=net0 \
 -device virtio-net-pci,netdev=net0 \
 -device virtio-blk-device,drive=hd0 \
 -drive file=openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw,format=raw,id=hd0