mirror of https://github.com/acidanthera/audk.git
202 lines
9.4 KiB
Plaintext
202 lines
9.4 KiB
Plaintext
#/** @file
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#
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# Copyright (c) 2011-2016, ARM Limited. All rights reserved.
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# Copyright (c) 2015, Intel Corporation. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = ArmPlatformPkg
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PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
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PACKAGE_VERSION = 0.1
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################################################################################
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#
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# Include Section - list of Include Paths that are provided by this package.
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# Comments are used for Keywords and Module Types.
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#
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# Supported Module Types:
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# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
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#
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################################################################################
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[Includes.common]
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Include # Root include for the package
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[Guids.common]
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gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
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#
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# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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#
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gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
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gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
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[PcdsFeatureFlag.common]
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# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
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gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
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gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
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gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
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# Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
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# we assume the OS will handle the FrameBuffer from the UEFI GOP information.
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gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
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# Enable Legacy Linux support in the BDS
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gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E
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[PcdsFixedAtBuild.common]
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gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
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gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
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# Stack for CPU Cores in Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
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# Stack for CPU Cores in Non Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
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gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
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# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
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# Boot Monitor FileSystem
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gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
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#
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# ARM Primecells
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#
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## SP804 DualTimer
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gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
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gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
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## SP805 Watchdog
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
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## PL011 UART
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gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
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gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
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gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
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gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
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## PL061 GPIO
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gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
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## PL111 Lcd & HdLcd
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gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
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gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
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## PL180 MCI
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gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
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gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
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#
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# BDS - Boot Manager
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#
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gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
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gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
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gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
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gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
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[PcdsFixedAtBuild.common,PcdsDynamic.common]
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## PL031 RealTimeClock
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gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
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gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
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#
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# Inclusive range of allowed PCI buses.
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#
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gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
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gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
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#
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# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
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# Note that "IO" is just another MMIO range that simulates IO space; there
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# are no special instructions to access it.
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#
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# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
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# specific to their containing address spaces. In order to get the physical
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# address for the CPU, for a given access, the respective translation value
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# has to be added.
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#
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# The translations always have to be initialized like this, using UINT64:
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#
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# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
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#
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# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
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# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
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# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
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#
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# because (a) the target address space (ie. the cpu-physical space) is
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# 64-bit, and (b) the translation values are meant as offsets for *modular*
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# arithmetic.
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#
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# Accordingly, the translation itself needs to be implemented as:
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#
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# UINT64 UntranslatedIoAddress; // input parameter
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# UINT32 UntranslatedMmio32Address; // input parameter
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# UINT64 UntranslatedMmio64Address; // input parameter
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#
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# UINT64 TranslatedIoAddress; // output parameter
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# UINT64 TranslatedMmio32Address; // output parameter
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# UINT64 TranslatedMmio64Address; // output parameter
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#
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# TranslatedIoAddress = UntranslatedIoAddress +
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# PcdPciIoTranslation;
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# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
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# PcdPciMmio32Translation;
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# TranslatedMmio64Address = UntranslatedMmio64Address +
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# PcdPciMmio64Translation;
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#
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# The modular arithmetic performed in UINT64 ensures that the translation
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# works correctly regardless of the relation between IoCpuBase and
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# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
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# PcdPciMmio64Base.
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#
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gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
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gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
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gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
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[PcdsFixedAtBuild.ARM]
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# Stack for CPU Cores in Secure Monitor Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
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[PcdsFixedAtBuild.AARCH64]
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# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
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# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
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# and PcdCPUCoreSecSecondaryStackSize
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
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