mirror of https://github.com/acidanthera/audk.git
183 lines
4.5 KiB
NASM
183 lines
4.5 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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;
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; Switch the stack from temporary memory to permanent memory.
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;
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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%include "PushPopRegsNasm.inc"
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; Page table related bits in CR0/CR4/EFER
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%define CR0_PG_MASK 0x80010000 ; CR0.PG and CR0.WP
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%define CR4_PG_MASK 0x10B0 ; CR4.PSE, CR4.PAE, CR4.PGE and CR4.LA57
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%define EFER_PG_MASK 0x800 ; EFER.NXE
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extern ASM_PFX(SwapStack)
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extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
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;------------------------------------------------------------------------------
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; UINT32
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; EFIAPI
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; Pei2LoaderSwitchStack (
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; VOID
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; )
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;------------------------------------------------------------------------------
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global ASM_PFX(Pei2LoaderSwitchStack)
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ASM_PFX(Pei2LoaderSwitchStack):
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xor rax, rax
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jmp ASM_PFX(FspSwitchStack)
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;------------------------------------------------------------------------------
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; UINT32
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; EFIAPI
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; Loader2PeiSwitchStack (
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; VOID
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; )
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;------------------------------------------------------------------------------
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global ASM_PFX(Loader2PeiSwitchStack)
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ASM_PFX(Loader2PeiSwitchStack):
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jmp ASM_PFX(FspSwitchStack)
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;------------------------------------------------------------------------------
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; UINT32
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; EFIAPI
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; FspSwitchStack (
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; VOID
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; )
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;------------------------------------------------------------------------------
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global ASM_PFX(FspSwitchStack)
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ASM_PFX(FspSwitchStack):
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; Save current contexts. The format must align with CONTEXT_STACK_64.
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push rdx ; Reserved QWORD for stack alignment
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push rdx ; ApiParam2
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push rcx ; ApiParam1
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push rax ; FspInfoHeader
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pushfq
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cli
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PUSHA_64
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;
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; Allocate 4x8 bytes on the stack.
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;
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sub rsp, 32
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lea rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
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mov dl, byte [rdx]
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cmp dl, 0
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jz SkipPagetableSave
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add rsp, 32
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; Save EFER MSR
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push rcx
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push rax
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mov rcx, 0xC0000080
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rdmsr
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shl rdx, 0x20
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or rdx, rax
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pop rax
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pop rcx
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push rdx
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; Save CR registers
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mov rdx, cr4
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push rdx
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mov rdx, cr3
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push rdx
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mov rdx, cr0
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push rdx
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SkipPagetableSave:
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sub rsp, 16
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sidt [rsp]
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; Load new stack
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mov rcx, rsp
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sub rsp, 0x20
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call ASM_PFX(SwapStack)
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add rsp, 0x20
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mov rsp, rax
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; Restore previous contexts
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lidt [rsp]
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add rsp, 16
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lea rax, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
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mov al, byte [rax]
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cmp al, 0
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jz SkipPagetableRestore
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; [rsp] stores new cr0
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; [rsp+8] stores new cr3
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; [rsp+16] stores new cr4
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; [rsp+24] stores new Efer
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;
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; When new EFER.NXE == 1, the restore flow is: EFER --> CRx
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; Otherwise: CRx --> EFER
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;
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; If NXE bit is changed to 1, change NXE before CR register
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; This is because Nx bit in page table entry in new CR3 will be invalid
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; if updating CR3 before EFER MSR.
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;
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mov rax, [rsp + 24]
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bt rax, 11
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jnc SkipEferLabel1
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; Restore EFER MSR
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mov ecx, 0xC0000080
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rdmsr
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and eax, ~EFER_PG_MASK
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mov ebx, [rsp + 24]
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and ebx, EFER_PG_MASK
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or eax, ebx
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wrmsr
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SkipEferLabel1:
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mov rbx, [rsp]
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mov rdx, cr0
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and rdx, ~CR0_PG_MASK
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and rbx, CR0_PG_MASK
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or rdx, rbx
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mov cr0, rdx
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mov rbx, [rsp + 8]
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mov cr3, rbx
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mov rbx, [rsp + 16]
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mov rdx, cr4
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and rdx, ~CR4_PG_MASK
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and rbx, CR4_PG_MASK
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or rdx, rbx
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mov cr4, rdx
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;
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; If NXE bit is changed to 0, change NXE after than CR regiser
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;
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mov rax, [rsp + 24]
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bt rax, 11
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jc SkipEferLabel2
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; Restore EFER MSR
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mov ecx, 0xC0000080
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rdmsr
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and eax, ~EFER_PG_MASK
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mov ebx, [rsp + 24]
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and ebx, EFER_PG_MASK
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or eax, ebx
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wrmsr
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SkipEferLabel2:
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SkipPagetableRestore:
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; pop page table related registers.
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add rsp, 32
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POPA_64
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popfq
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add rsp, 32 ; FspInfoHeader + ApiParam[2] + Reserved QWORD
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ret
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