mirror of https://github.com/acidanthera/audk.git
208 lines
4.7 KiB
C
208 lines
4.7 KiB
C
/*++
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Copyright (c) 2006 - 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PciCommand.c
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Abstract:
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PCI Bus Driver
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Revision History
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--*/
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#include "pcibus.h"
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EFI_STATUS
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PciOperateRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command,
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IN UINT8 Offset,
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IN UINT8 Operation,
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OUT UINT16 *PtrCommand
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciIoDevice - add argument and description to function comment
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// TODO: Command - add argument and description to function comment
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// TODO: Offset - add argument and description to function comment
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// TODO: Operation - add argument and description to function comment
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// TODO: PtrCommand - add argument and description to function comment
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{
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UINT16 OldCommand;
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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if (Operation != EFI_SET_REGISTER) {
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Status = PciIoRead (
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PciIo,
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EfiPciIoWidthUint16,
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Offset,
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1,
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&OldCommand
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);
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if (Operation == EFI_GET_REGISTER) {
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*PtrCommand = OldCommand;
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return Status;
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}
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}
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if (Operation == EFI_ENABLE_REGISTER) {
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OldCommand = (UINT16) (OldCommand | Command);
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} else if (Operation == EFI_DISABLE_REGISTER) {
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OldCommand = (UINT16) (OldCommand & ~(Command));
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} else {
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OldCommand = Command;
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}
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return PciIoWrite (
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PciIo,
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EfiPciIoWidthUint16,
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Offset,
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1,
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&OldCommand
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);
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}
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BOOLEAN
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PciCapabilitySupport (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciIoDevice - add argument and description to function comment
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{
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if (PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) {
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return TRUE;
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}
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return FALSE;
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}
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EFI_STATUS
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LocateCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset,
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OUT UINT8 *NextRegBlock OPTIONAL
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)
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/*++
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Routine Description:
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Locate cap reg.
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Arguments:
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PciIoDevice - A pointer to the PCI_IO_DEVICE.
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CapId - The cap ID.
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Offset - A pointer to the offset.
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NextRegBlock - A pointer to the next block.
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Returns:
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None
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--*/
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// TODO: EFI_UNSUPPORTED - add return value to function comment
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// TODO: EFI_SUCCESS - add return value to function comment
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// TODO: EFI_NOT_FOUND - add return value to function comment
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{
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UINT8 CapabilityPtr;
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UINT16 CapabilityEntry;
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UINT8 CapabilityID;
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//
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// To check the cpability of this device supports
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//
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if (!PciCapabilitySupport (PciIoDevice)) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = 0;
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if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
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PciIoRead (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint8,
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EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
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1,
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&CapabilityPtr
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);
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} else {
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PciIoRead (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint8,
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EFI_PCI_CAPABILITY_PTR,
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1,
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&CapabilityPtr
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);
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}
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}
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while (CapabilityPtr > 0x3F) {
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//
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// Mask it to DWORD alignment per PCI spec
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//
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CapabilityPtr &= 0xFC;
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PciIoRead (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint16,
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CapabilityPtr,
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1,
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&CapabilityEntry
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);
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CapabilityID = (UINT8) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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if (NextRegBlock != NULL) {
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*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_SUCCESS;
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}
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CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_NOT_FOUND;
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}
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