mirror of https://github.com/acidanthera/audk.git
158 lines
2.9 KiB
C
158 lines
2.9 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __AARCH64_H__
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#define __AARCH64_H__
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#include <Chipset/AArch64Mmu.h>
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#include <Chipset/ArmArchTimer.h>
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// ARM Interrupt ID in Exception Table
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#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_TTA_EN (1UL << 28)
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#define CPACR_FPEN_EL1 (1UL << 20)
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#define CPACR_FPEN_FULL (3UL << 20)
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#define CPACR_CP_FULL_ACCESS 0x300000
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// Coprocessor Trap Register (CPTR)
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#define AARCH64_CPTR_TFP (1 << 10)
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// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
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#define AARCH64_PFR0_FP (0xF << 16)
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_AEMv8 0xD0F
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#define ARM_CPU_TYPE_A15 0xC0F
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#define ARM_CPU_TYPE_A9 0xC09
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#define ARM_CPU_TYPE_A5 0xC05
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// Hypervisor Configuration Register
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#define ARM_HCR_FMO BIT3
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#define ARM_HCR_IMO BIT4
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#define ARM_HCR_AMO BIT5
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#define ARM_HCR_TGE BIT27
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// AArch64 Exception Level
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#define AARCH64_EL3 0xC
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#define AARCH64_EL2 0x8
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#define AARCH64_EL1 0x4
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#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadCbar (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw (
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UINTN Value
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);
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UINTN
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EFIAPI
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ArmGetTCR (
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VOID
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);
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VOID
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EFIAPI
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ArmSetTCR (
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UINTN Value
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);
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UINTN
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EFIAPI
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ArmGetMAIR (
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VOID
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);
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VOID
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EFIAPI
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ArmSetMAIR (
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UINTN Value
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);
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VOID
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EFIAPI
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ArmDisableAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableAllExceptions (
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VOID
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);
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VOID
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ArmWriteHcr (
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IN UINTN Hcr
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);
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UINTN
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ArmReadCurrentEL (
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VOID
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);
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UINT64
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PageAttributeToGcdAttribute (
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IN UINT64 PageAttributes
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);
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UINT64
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GcdAttributeToPageAttribute (
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IN UINT64 GcdAttributes
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);
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UINTN
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ArmWriteCptr (
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IN UINT64 Cptr
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);
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#endif // __AARCH64_H__
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