mirror of https://github.com/acidanthera/audk.git
349 lines
11 KiB
C
349 lines
11 KiB
C
/** @file
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Graphics Output Protocol functions for the QEMU video controller.
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Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Qemu.h"
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///
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/// Generic Attribute Controller Register Settings
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///
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UINT8 AttributeController[21] = {
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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0x41, 0x00, 0x0F, 0x00, 0x00
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};
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///
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/// Generic Graphics Controller Register Settings
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///
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UINT8 GraphicsController[9] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF
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};
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//
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// 640 x 480 x 256 color @ 60 Hertz
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//
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UINT8 Crtc_640_480_256_60[28] = {
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0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,
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0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0xe1, 0x83, 0xdf, 0x50, 0x00, 0xe7, 0x04, 0xe3,
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0xff, 0x00, 0x00, 0x22
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};
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UINT8 Crtc_640_480_32bpp_60[28] = {
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0x5d, 0x4f, 0x50, 0x82, 0x53, 0x9f, 0x00, 0x3e,
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0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0xe1, 0x83, 0xdf, 0x40, 0x00, 0xe7, 0x04, 0xe3,
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0xff, 0x00, 0x00, 0x32
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};
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UINT16 Seq_640_480_256_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e
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};
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UINT16 Seq_640_480_32bpp_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x7e0e, 0x2b1b, 0x2f1c, 0x301d, 0x331e
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};
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//
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// 800 x 600 x 256 color @ 60 Hertz
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//
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UINT8 Crtc_800_600_256_60[28] = {
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0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x58, 0x8C, 0x57, 0x64, 0x00, 0x5F, 0x91, 0xE3,
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0xFF, 0x00, 0x00, 0x22
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};
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UINT8 Crtc_800_600_32bpp_60[28] = {
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0x7F, 0x63, 0x64, 0x80, 0x6B, 0x1B, 0x72, 0xF0,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x58, 0x8C, 0x57, 0x90, 0x00, 0x5F, 0x91, 0xE3,
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0xFF, 0x00, 0x00, 0x32
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};
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UINT16 Seq_800_600_256_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e
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};
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UINT16 Seq_800_600_32bpp_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x510e, 0x2b1b, 0x2f1c, 0x301d, 0x3a1e
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};
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UINT8 Crtc_960_720_32bpp_60[28] = {
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0xA3, 0x77, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x02, 0x88, 0xCF, 0xe0, 0x00, 0x00, 0x64, 0xE3,
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0xFF, 0x4A, 0x00, 0x32
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};
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UINT16 Seq_960_720_32bpp_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
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};
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//
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// 1024 x 768 x 256 color @ 60 Hertz
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//
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UINT8 Crtc_1024_768_256_60[28] = {
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0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
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0xFF, 0x4A, 0x00, 0x22
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};
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UINT16 Seq_1024_768_256_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1107, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
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};
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//
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// 1024 x 768 x 24-bit color @ 60 Hertz
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//
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UINT8 Crtc_1024_768_24bpp_60[28] = {
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0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x02, 0x88, 0xFF, 0x80, 0x00, 0x00, 0x24, 0xE3,
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0xFF, 0x4A, 0x00, 0x32
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};
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UINT16 Seq_1024_768_24bpp_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1507, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
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};
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UINT8 Crtc_1024_768_32bpp_60[28] = {
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0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xFD,
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0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x02, 0x88, 0xFF, 0xe0, 0x00, 0x00, 0x64, 0xE3,
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0xFF, 0x4A, 0x00, 0x32
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};
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UINT16 Seq_1024_768_32bpp_60[15] = {
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0x0100, 0x0101, 0x0f02, 0x0003, 0x0e04, 0x1907, 0x0008, 0x4a0b,
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0x5b0c, 0x450d, 0x760e, 0x2b1b, 0x2f1c, 0x301d, 0x341e
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};
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///
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/// Table of supported video modes
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///
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QEMU_VIDEO_CIRRUS_MODES QemuVideoCirrusModes[] = {
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// { 640, 480, 8, Crtc_640_480_256_60, Seq_640_480_256_60, 0xe3 },
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// { 800, 600, 8, Crtc_800_600_256_60, Seq_800_600_256_60, 0xef },
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{ 640, 480, 32, Crtc_640_480_32bpp_60, Seq_640_480_32bpp_60, 0xef },
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{ 800, 600, 32, Crtc_800_600_32bpp_60, Seq_800_600_32bpp_60, 0xef },
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// { 1024, 768, 8, Crtc_1024_768_256_60, Seq_1024_768_256_60, 0xef }
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{ 1024, 768, 24, Crtc_1024_768_24bpp_60, Seq_1024_768_24bpp_60, 0xef }
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// { 1024, 768, 32, Crtc_1024_768_32bpp_60, Seq_1024_768_32bpp_60, 0xef }
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// { 960, 720, 32, Crtc_960_720_32bpp_60, Seq_1024_768_32bpp_60, 0xef }
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};
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#define QEMU_VIDEO_CIRRUS_MODE_COUNT \
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(ARRAY_SIZE (QemuVideoCirrusModes))
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/**
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Construct the valid video modes for QemuVideo.
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**/
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EFI_STATUS
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QemuVideoCirrusModeSetup (
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QEMU_VIDEO_PRIVATE_DATA *Private
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)
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{
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UINT32 Index;
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QEMU_VIDEO_MODE_DATA *ModeData;
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QEMU_VIDEO_CIRRUS_MODES *VideoMode;
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//
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// Setup Video Modes
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//
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Private->ModeData = AllocatePool (
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sizeof (Private->ModeData[0]) * QEMU_VIDEO_CIRRUS_MODE_COUNT
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);
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if (Private->ModeData == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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ModeData = Private->ModeData;
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VideoMode = &QemuVideoCirrusModes[0];
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for (Index = 0; Index < QEMU_VIDEO_CIRRUS_MODE_COUNT; Index ++) {
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ModeData->InternalModeIndex = Index;
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ModeData->HorizontalResolution = VideoMode->Width;
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ModeData->VerticalResolution = VideoMode->Height;
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ModeData->ColorDepth = VideoMode->ColorDepth;
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DEBUG ((EFI_D_INFO,
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"Adding Mode %d as Cirrus Internal Mode %d: %dx%d, %d-bit\n",
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(INT32) (ModeData - Private->ModeData),
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ModeData->InternalModeIndex,
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ModeData->HorizontalResolution,
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ModeData->VerticalResolution,
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ModeData->ColorDepth
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));
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ModeData ++ ;
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VideoMode ++;
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}
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Private->MaxMode = ModeData - Private->ModeData;
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return EFI_SUCCESS;
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}
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///
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/// Table of supported video modes
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///
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QEMU_VIDEO_BOCHS_MODES QemuVideoBochsModes[] = {
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{ 640, 480, 32 },
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{ 800, 480, 32 },
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{ 800, 600, 32 },
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{ 832, 624, 32 },
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{ 960, 640, 32 },
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{ 1024, 600, 32 },
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{ 1024, 768, 32 },
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{ 1152, 864, 32 },
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{ 1152, 870, 32 },
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{ 1280, 720, 32 },
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{ 1280, 760, 32 },
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{ 1280, 768, 32 },
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{ 1280, 800, 32 },
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{ 1280, 960, 32 },
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{ 1280, 1024, 32 },
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{ 1360, 768, 32 },
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{ 1366, 768, 32 },
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{ 1400, 1050, 32 },
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{ 1440, 900, 32 },
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{ 1600, 900, 32 },
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{ 1600, 1200, 32 },
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{ 1680, 1050, 32 },
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{ 1920, 1080, 32 },
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{ 1920, 1200, 32 },
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{ 1920, 1440, 32 },
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{ 2000, 2000, 32 },
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{ 2048, 1536, 32 },
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{ 2048, 2048, 32 },
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{ 2560, 1440, 32 },
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{ 2560, 1600, 32 },
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{ 2560, 2048, 32 },
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{ 2800, 2100, 32 },
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{ 3200, 2400, 32 },
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{ 3840, 2160, 32 },
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{ 4096, 2160, 32 },
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{ 7680, 4320, 32 },
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{ 8192, 4320, 32 }
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};
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#define QEMU_VIDEO_BOCHS_MODE_COUNT \
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(ARRAY_SIZE (QemuVideoBochsModes))
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EFI_STATUS
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QemuVideoBochsModeSetup (
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QEMU_VIDEO_PRIVATE_DATA *Private,
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BOOLEAN IsQxl
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)
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{
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UINT32 AvailableFbSize;
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UINT32 Index;
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QEMU_VIDEO_MODE_DATA *ModeData;
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QEMU_VIDEO_BOCHS_MODES *VideoMode;
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//
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// Fetch the available framebuffer size.
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//
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// VBE_DISPI_INDEX_VIDEO_MEMORY_64K is expected to return the size of the
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// drawable framebuffer. Up to and including qemu-2.1 however it used to
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// return the size of PCI BAR 0 (ie. the full video RAM size).
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//
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// On stdvga the two concepts coincide with each other; the full memory size
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// is usable for drawing.
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//
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// On QXL however, only a leading segment, "surface 0", can be used for
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// drawing; the rest of the video memory is used for the QXL guest-host
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// protocol. VBE_DISPI_INDEX_VIDEO_MEMORY_64K should report the size of
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// "surface 0", but since it doesn't (up to and including qemu-2.1), we
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// retrieve the size of the drawable portion from a field in the QXL ROM BAR,
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// where it is also available.
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//
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if (IsQxl) {
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UINT32 Signature;
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UINT32 DrawStart;
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Signature = 0;
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DrawStart = 0xFFFFFFFF;
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AvailableFbSize = 0;
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if (EFI_ERROR (
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Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
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PCI_BAR_IDX2, 0, 1, &Signature)) ||
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Signature != SIGNATURE_32 ('Q', 'X', 'R', 'O') ||
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EFI_ERROR (
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Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
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PCI_BAR_IDX2, 36, 1, &DrawStart)) ||
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DrawStart != 0 ||
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EFI_ERROR (
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Private->PciIo->Mem.Read (Private->PciIo, EfiPciIoWidthUint32,
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PCI_BAR_IDX2, 40, 1, &AvailableFbSize))) {
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DEBUG ((EFI_D_ERROR, "%a: can't read size of drawable buffer from QXL "
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"ROM\n", __FUNCTION__));
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return EFI_NOT_FOUND;
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}
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} else {
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AvailableFbSize = BochsRead (Private, VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
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AvailableFbSize *= SIZE_64KB;
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}
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DEBUG ((EFI_D_INFO, "%a: AvailableFbSize=0x%x\n", __FUNCTION__,
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AvailableFbSize));
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//
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// Setup Video Modes
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//
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Private->ModeData = AllocatePool (
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sizeof (Private->ModeData[0]) * QEMU_VIDEO_BOCHS_MODE_COUNT
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);
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if (Private->ModeData == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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ModeData = Private->ModeData;
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VideoMode = &QemuVideoBochsModes[0];
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for (Index = 0; Index < QEMU_VIDEO_BOCHS_MODE_COUNT; Index ++) {
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UINTN RequiredFbSize;
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ASSERT (VideoMode->ColorDepth % 8 == 0);
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RequiredFbSize = (UINTN) VideoMode->Width * VideoMode->Height *
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(VideoMode->ColorDepth / 8);
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if (RequiredFbSize <= AvailableFbSize) {
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ModeData->InternalModeIndex = Index;
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ModeData->HorizontalResolution = VideoMode->Width;
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ModeData->VerticalResolution = VideoMode->Height;
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ModeData->ColorDepth = VideoMode->ColorDepth;
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DEBUG ((EFI_D_INFO,
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"Adding Mode %d as Bochs Internal Mode %d: %dx%d, %d-bit\n",
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(INT32) (ModeData - Private->ModeData),
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ModeData->InternalModeIndex,
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ModeData->HorizontalResolution,
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ModeData->VerticalResolution,
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ModeData->ColorDepth
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));
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ModeData ++ ;
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}
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VideoMode ++;
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}
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Private->MaxMode = ModeData - Private->ModeData;
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return EFI_SUCCESS;
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}
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