mirror of
https://github.com/acidanthera/audk.git
synced 2025-12-16 01:55:29 +01:00
3ee23713e1
The Coresight Embedded Trace Extension (ETE) feature can be detected by the platform firmware by examining the debug feature register ID_AA64DFR0_EL1.TraceVer field. The platform configuration manager can then describe the ETE by creating CM_ARM_ET_INFO object(s) and referencing these in CM_ARM_GICC_INFO.EtToken. The 'Table 3: Compatible IDs for architected CoreSight components' in the 'ACPI for CoreSight 1.2 Platform Design Document' specifies the HID value for Coresight ETE and CoreSight Embedded Trace Macrocell (ETM) v4.x as ARMH C500. Therefore, update the SsdtCpuTopologyGenerator to add an ETE device to the CPU node in the AML CPU hierarchy so that an OS can utilise this information. Note: Although ETE and ETM share the same HID, ETE has a system register interfaces, unlike ETM which requires memory mapped registers. Since this patch aims to support ETE, the AML description does not describe any memory mapped registers. However, support for ETM can be added in the future. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>