mirror of https://github.com/acidanthera/audk.git
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/** @file
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Platform Pcie Helper Lib.
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Copyright (c) 2013 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CommonHeader.h"
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//
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// Routines local to this source module.
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//
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VOID
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LegacyGpioSetLevel (
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IN CONST UINT32 LevelRegOffset,
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IN CONST UINT32 GpioNum,
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IN CONST BOOLEAN HighLevel
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)
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{
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UINT32 RegValue;
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UINT32 GpioBaseAddress;
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UINT32 GpioNumMask;
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GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
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ASSERT (GpioBaseAddress > 0);
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RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
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GpioNumMask = (1 << GpioNum);
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if (HighLevel) {
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RegValue |= (GpioNumMask);
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} else {
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RegValue &= ~(GpioNumMask);
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}
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IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue);
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}
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//
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// Routines exported by this component.
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//
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/**
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Platform assert PCI express PERST# signal.
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@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
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**/
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VOID
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EFIAPI
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PlatformPERSTAssert (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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if (PlatformType == GalileoGen2) {
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LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
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} else {
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LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
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}
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}
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/**
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Platform de assert PCI express PERST# signal.
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@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
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**/
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VOID
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EFIAPI
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PlatformPERSTDeAssert (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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if (PlatformType == GalileoGen2) {
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LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
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} else {
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LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
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}
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}
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/** Early initialisation of the PCIe controller.
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@param PlatformType See EFI_PLATFORM_TYPE enum definitions.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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PlatformPciExpressEarlyInit (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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//
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// Release and wait for PCI controller to come out of reset.
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//
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SocUnitReleasePcieControllerPreWaitPllLock (PlatformType);
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MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK);
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SocUnitReleasePcieControllerPostPllLock (PlatformType);
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//
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// Early PCIe initialisation
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//
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SocUnitEarlyInitialisation ();
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//
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// Do North cluster early PCIe init.
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//
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PciExpressEarlyInit ();
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return EFI_SUCCESS;
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}
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