mirror of https://github.com/acidanthera/audk.git
165 lines
4.2 KiB
C
Executable File
165 lines
4.2 KiB
C
Executable File
/** @file
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C Entry point for the SEC. First C code after the reset vector.
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/PrePiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/DebugAgentLib.h>
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#include <Ppi/GuidedSectionExtraction.h>
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#include <Guid/LzmaDecompress.h>
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#include <ArmEb/ArmEb.h>
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#include "LzmaDecompress.h"
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VOID
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EFIAPI
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_ModuleEntryPoint(
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VOID
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);
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CHAR8 *
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DeCygwinPathIfNeeded (
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IN CHAR8 *Name
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);
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RETURN_STATUS
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EFIAPI
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SerialPortInitialize (
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VOID
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);
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VOID
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UartInit (
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VOID
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)
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{
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// SEC phase needs to run library constructors by hand.
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// This assumes we are linked agains the SerialLib
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// In non SEC modules the init call is in autogenerated code.
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SerialPortInitialize ();
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}
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VOID
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TimerInit (
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VOID
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)
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{
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Enable
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MmioOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER2_EN);
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// configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
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MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
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// preload the timer count register
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MmioWrite32 (EB_SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
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// enable the timer
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MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
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}
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VOID
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InitCache (
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IN UINT32 MemoryBase,
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IN UINT32 MemoryLength
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);
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EFI_STATUS
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EFIAPI
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ExtractGuidedSectionLibConstructor (
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VOID
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);
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EFI_STATUS
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EFIAPI
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LzmaDecompressLibConstructor (
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VOID
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);
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VOID
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CEntryPoint (
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IN VOID *MemoryBase,
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IN UINTN MemorySize,
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IN VOID *StackBase,
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IN UINTN StackSize
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)
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{
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VOID *HobBase;
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// HOB list is at bottom of stack area
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// Stack grows from top-to-bottom towards HOB list
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HobBase = (VOID *)StackBase;
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CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);
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// Turn off remapping NOR to 0. We can will now see DRAM in low memory
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MmioOr32 (0x10001000 ,BIT8); //EB_SP810_CTRL_BASE
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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// Initialize CPU cache
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InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);
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// Add memory allocation hob for relocated FD
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BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);
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// Add the FVs to the hob list
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BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));
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// Start talking
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UartInit ();
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InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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DEBUG ((EFI_D_ERROR, "UART Enabled\n"));
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// Start up a free running timer so that the timer lib will work
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TimerInit ();
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// SEC phase needs to run library constructors by hand.
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ExtractGuidedSectionLibConstructor ();
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LzmaDecompressLibConstructor ();
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// Build HOBs to pass up our version of stuff the DXE Core needs to save space
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BuildPeCoffLoaderHob ();
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BuildExtractSectionHob (
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&gLzmaCustomDecompressGuid,
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LzmaGuidedSectionGetInfo,
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LzmaGuidedSectionExtraction
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);
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// Assume the FV that contains the SEC (our code) also contains a compressed FV.
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DecompressFirstFv ();
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// Load the DXE Core and transfer control to it
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LoadDxeCoreFromFv (NULL, 0);
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// DXE Core should always load and never return
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ASSERT (FALSE);
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}
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