jgong5 40e8cca588 Fix the SMRAM caching range base and size. The original code uses the biggest SMRAM range base and size to set the cache attribute by gDS->SetMemorySpaceAttributes(). This is not correct because the platform code might split the TSEG into several ranges. The fix searches and joins all the adjacent ranges to the biggest SMRAM range into a cacheable range so that TSEG can be cached as a whole. ... git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10213 6f19259b-4bc3-4df7-8a09-765794883524		2010-03-09 05:47:41 +00:00
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Dxe	Minor bug fix and robustness check improvement.	2010-03-03 09:40:16 +00:00
DxeIplPeim	update DxeIpl to use EFI_S3_RESUME2_PPI instead of EFI_S3_RESUME_PPI	2010-03-01 07:11:28 +00:00
Pei	Fix a bug in load modules at fixed address which may potentially impact OS S3.	2010-03-04 03:16:55 +00:00
PiSmmCore	Fix the SMRAM caching range base and size. The original code uses the biggest SMRAM range base and size to set the cache attribute by gDS->SetMemorySpaceAttributes(). This is not correct because the platform code might split the TSEG into several ranges. The fix searches and joins all the adjacent ranges to the biggest SMRAM range into a cacheable range so that TSEG can be cached as a whole.	2010-03-09 05:47:41 +00:00
RuntimeDxe	1. Correct File header to ## @file	2010-02-24 00:21:16 +00:00