mirror of https://github.com/acidanthera/audk.git
304 lines
12 KiB
C
304 lines
12 KiB
C
/** @file
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IA32/x64 architecture specific definitions needed by debug transfer protocol.It is only
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intended to be used by Debug related module implementation.
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Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __PROCESSOR_CONTEXT_H__
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#define __PROCESSOR_CONTEXT_H__
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//
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// IA-32/x64 processor register index table
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//
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#define SOFT_DEBUGGER_REGISTER_DR0 0x00
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#define SOFT_DEBUGGER_REGISTER_DR1 0x01
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#define SOFT_DEBUGGER_REGISTER_DR2 0x02
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#define SOFT_DEBUGGER_REGISTER_DR3 0x03
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#define SOFT_DEBUGGER_REGISTER_DR6 0x04
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#define SOFT_DEBUGGER_REGISTER_DR7 0x05
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#define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06
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#define SOFT_DEBUGGER_REGISTER_LDTR 0x07
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#define SOFT_DEBUGGER_REGISTER_TR 0x08
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#define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR
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#define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR
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#define SOFT_DEBUGGER_REGISTER_EIP 0x0D
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#define SOFT_DEBUGGER_REGISTER_GS 0x0E
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#define SOFT_DEBUGGER_REGISTER_FS 0x0F
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#define SOFT_DEBUGGER_REGISTER_ES 0x10
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#define SOFT_DEBUGGER_REGISTER_DS 0x11
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#define SOFT_DEBUGGER_REGISTER_CS 0x12
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#define SOFT_DEBUGGER_REGISTER_SS 0x13
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#define SOFT_DEBUGGER_REGISTER_CR0 0x14
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#define SOFT_DEBUGGER_REGISTER_CR1 0x15
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#define SOFT_DEBUGGER_REGISTER_CR2 0x16
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#define SOFT_DEBUGGER_REGISTER_CR3 0x17
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#define SOFT_DEBUGGER_REGISTER_CR4 0x18
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#define SOFT_DEBUGGER_REGISTER_DI 0x19
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#define SOFT_DEBUGGER_REGISTER_SI 0x1A
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#define SOFT_DEBUGGER_REGISTER_BP 0x1B
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#define SOFT_DEBUGGER_REGISTER_SP 0x1C
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#define SOFT_DEBUGGER_REGISTER_DX 0x1D
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#define SOFT_DEBUGGER_REGISTER_CX 0x1E
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#define SOFT_DEBUGGER_REGISTER_BX 0x1F
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#define SOFT_DEBUGGER_REGISTER_AX 0x20
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//
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// This below registers are only available for x64 (not valid for Ia32 mode)
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//
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#define SOFT_DEBUGGER_REGISTER_CR8 0x21
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#define SOFT_DEBUGGER_REGISTER_R8 0x22
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#define SOFT_DEBUGGER_REGISTER_R9 0x23
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#define SOFT_DEBUGGER_REGISTER_R10 0x24
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#define SOFT_DEBUGGER_REGISTER_R11 0x25
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#define SOFT_DEBUGGER_REGISTER_R12 0x26
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#define SOFT_DEBUGGER_REGISTER_R13 0x27
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#define SOFT_DEBUGGER_REGISTER_R14 0x28
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#define SOFT_DEBUGGER_REGISTER_R15 0x29
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//
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// This below registers are FP / MMX / XMM registers
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//
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#define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30
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#define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00)
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#define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01)
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#define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02)
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#define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03)
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#define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04)
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#define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05)
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#define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06)
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#define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08)
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#define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09)
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#define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A)
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#define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B)
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#define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C)
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#define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D)
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#define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E)
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#define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F)
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#define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10)
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#define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11)
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#define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12)
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#define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13)
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#define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14)
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#define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15)
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#define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16)
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#define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17)
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#define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18)
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#define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19)
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#define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A)
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#define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B)
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#define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C)
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#define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D)
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#define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E)
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#define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F)
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#define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20)
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#define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21)
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#define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22)
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#define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23)
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#define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24)
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#define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25)
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#define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26)
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#define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27)
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#define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28)
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#define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29)
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#define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7
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#define SOFT_DEBUGGER_MSR_EFER (0xC0000080)
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#pragma pack(1)
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///
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/// FXSAVE_STATE
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/// FP / MMX / XMM registers (see fxrstor instruction definition)
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///
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typedef struct {
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UINT16 Fcw;
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UINT16 Fsw;
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UINT16 Ftw;
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UINT16 Opcode;
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UINT32 Eip;
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UINT16 Cs;
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UINT16 Reserved1;
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UINT32 DataOffset;
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UINT16 Ds;
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UINT8 Reserved2[2];
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UINT32 Mxcsr;
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UINT32 Mxcsr_Mask;
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UINT8 St0Mm0[10];
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UINT8 Reserved3[6];
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UINT8 St1Mm1[10];
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UINT8 Reserved4[6];
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UINT8 St2Mm2[10];
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UINT8 Reserved5[6];
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UINT8 St3Mm3[10];
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UINT8 Reserved6[6];
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UINT8 St4Mm4[10];
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UINT8 Reserved7[6];
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UINT8 St5Mm5[10];
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UINT8 Reserved8[6];
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UINT8 St6Mm6[10];
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UINT8 Reserved9[6];
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UINT8 St7Mm7[10];
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UINT8 Reserved10[6];
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UINT8 Xmm0[16];
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UINT8 Xmm1[16];
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UINT8 Xmm2[16];
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UINT8 Xmm3[16];
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UINT8 Xmm4[16];
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UINT8 Xmm5[16];
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UINT8 Xmm6[16];
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UINT8 Xmm7[16];
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UINT8 Reserved11[14 * 16];
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} DEBUG_DATA_IA32_FX_SAVE_STATE;
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///
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/// IA-32 processor context definition
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///
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typedef struct {
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UINT32 ExceptionData;
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DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
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UINT32 Dr0;
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UINT32 Dr1;
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UINT32 Dr2;
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UINT32 Dr3;
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UINT32 Dr6;
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UINT32 Dr7;
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UINT32 Eflags;
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UINT32 Ldtr;
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UINT32 Tr;
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UINT32 Gdtr[2];
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UINT32 Idtr[2];
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UINT32 Eip;
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UINT32 Gs;
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UINT32 Fs;
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UINT32 Es;
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UINT32 Ds;
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UINT32 Cs;
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UINT32 Ss;
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UINT32 Cr0;
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UINT32 Cr1; ///< Reserved
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UINT32 Cr2;
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UINT32 Cr3;
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UINT32 Cr4;
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UINT32 Edi;
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UINT32 Esi;
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UINT32 Ebp;
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UINT32 Esp;
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UINT32 Edx;
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UINT32 Ecx;
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UINT32 Ebx;
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UINT32 Eax;
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} DEBUG_DATA_IA32_SYSTEM_CONTEXT;
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///
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/// FXSAVE_STATE
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/// FP / MMX / XMM registers (see fxrstor instruction definition)
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///
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typedef struct {
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UINT16 Fcw;
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UINT16 Fsw;
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UINT16 Ftw;
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UINT16 Opcode;
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UINT32 Eip;
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UINT16 Cs;
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UINT16 Reserved1;
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UINT32 DataOffset;
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UINT16 Ds;
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UINT8 Reserved2[2];
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UINT32 Mxcsr;
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UINT32 Mxcsr_Mask;
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UINT8 St0Mm0[10];
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UINT8 Reserved3[6];
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UINT8 St1Mm1[10];
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UINT8 Reserved4[6];
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UINT8 St2Mm2[10];
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UINT8 Reserved5[6];
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UINT8 St3Mm3[10];
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UINT8 Reserved6[6];
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UINT8 St4Mm4[10];
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UINT8 Reserved7[6];
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UINT8 St5Mm5[10];
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UINT8 Reserved8[6];
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UINT8 St6Mm6[10];
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UINT8 Reserved9[6];
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UINT8 St7Mm7[10];
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UINT8 Reserved10[6];
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UINT8 Xmm0[16];
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UINT8 Xmm1[16];
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UINT8 Xmm2[16];
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UINT8 Xmm3[16];
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UINT8 Xmm4[16];
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UINT8 Xmm5[16];
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UINT8 Xmm6[16];
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UINT8 Xmm7[16];
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UINT8 Xmm8[16];
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UINT8 Xmm9[16];
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UINT8 Xmm10[16];
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UINT8 Xmm11[16];
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UINT8 Xmm12[16];
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UINT8 Xmm13[16];
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UINT8 Xmm14[16];
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UINT8 Xmm15[16];
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UINT8 Reserved11[6 * 16];
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} DEBUG_DATA_X64_FX_SAVE_STATE;
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///
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/// x64 processor context definition
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///
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typedef struct {
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UINT64 ExceptionData;
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DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;
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UINT64 Dr0;
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UINT64 Dr1;
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UINT64 Dr2;
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UINT64 Dr3;
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UINT64 Dr6;
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UINT64 Dr7;
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UINT64 Eflags;
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UINT64 Ldtr;
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UINT64 Tr;
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UINT64 Gdtr[2];
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UINT64 Idtr[2];
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UINT64 Eip;
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UINT64 Gs;
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UINT64 Fs;
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UINT64 Es;
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UINT64 Ds;
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UINT64 Cs;
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UINT64 Ss;
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UINT64 Cr0;
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UINT64 Cr1; ///< Reserved
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UINT64 Cr2;
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UINT64 Cr3;
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UINT64 Cr4;
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UINT64 Rdi;
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UINT64 Rsi;
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UINT64 Rbp;
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UINT64 Rsp;
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UINT64 Rdx;
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UINT64 Rcx;
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UINT64 Rbx;
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UINT64 Rax;
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UINT64 Cr8;
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UINT64 R8;
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UINT64 R9;
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UINT64 R10;
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UINT64 R11;
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UINT64 R12;
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UINT64 R13;
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UINT64 R14;
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UINT64 R15;
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} DEBUG_DATA_X64_SYSTEM_CONTEXT;
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#pragma pack()
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#endif
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