mirror of https://github.com/acidanthera/audk.git
882 lines
22 KiB
C
882 lines
22 KiB
C
/*++
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Copyright (c) 2006, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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LightPciLib.c
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Abstract:
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Light PCI Bus Driver Lib file
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It abstracts some functions that can be different
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between light PCI bus driver and full PCI bus driver
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Revision History
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--*/
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#include "pcibus.h"
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//
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// Light PCI bus driver woundn't support hotplug device
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// So just return
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//
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VOID
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InstallHotPlugRequestProtocol (
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IN EFI_STATUS *Status
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: Status - add argument and description to function comment
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{
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return ;
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}
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//
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// Light PCI bus driver woundn't support hotplug device
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// So just skip install this GUID
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//
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VOID
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InstallPciHotplugGuid (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciIoDevice - add argument and description to function comment
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{
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return ;
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}
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//
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// Light PCI bus driver woundn't support hotplug device
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// So just skip uninstall the GUID
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//
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VOID
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UninstallPciHotplugGuid (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciIoDevice - add argument and description to function comment
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{
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return ;
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}
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//
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// Light PCI bus driver woundn't support PCCard
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// So it needn't get the bar of CardBus
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//
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VOID
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GetBackPcCardBar (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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TODO: Add function description
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Arguments:
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PciIoDevice - TODO: add argument description
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Returns:
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TODO: add return values
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--*/
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{
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return ;
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}
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//
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// Light PCI bus driver woundn't support resource reallocation
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// So just return
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//
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EFI_STATUS
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RemoveRejectedPciDevices (
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EFI_HANDLE RootBridgeHandle,
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IN PCI_IO_DEVICE *Bridge
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)
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/*++
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Routine Description:
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TODO: Add function description
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Arguments:
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RootBridgeHandle - TODO: add argument description
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Bridge - TODO: add argument description
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Returns:
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EFI_SUCCESS - TODO: Add description for return value
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--*/
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{
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return EFI_SUCCESS;
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}
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//
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// Light PCI bus driver woundn't support resource reallocation
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// Simplified the code
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//
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EFI_STATUS
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PciHostBridgeResourceAllocator (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
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)
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/*++
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Routine Description:
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Arguments:
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Returns:
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None
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--*/
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// TODO: PciResAlloc - add argument and description to function comment
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// TODO: EFI_NOT_FOUND - add return value to function comment
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// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
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// TODO: EFI_NOT_FOUND - add return value to function comment
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// TODO: EFI_SUCCESS - add return value to function comment
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{
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PCI_IO_DEVICE *RootBridgeDev;
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EFI_HANDLE RootBridgeHandle;
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VOID *AcpiConfig;
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EFI_STATUS Status;
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UINT64 IoBase;
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UINT64 Mem32Base;
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UINT64 PMem32Base;
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UINT64 Mem64Base;
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UINT64 PMem64Base;
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UINT64 MaxOptionRomSize;
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PCI_RESOURCE_NODE *IoBridge;
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PCI_RESOURCE_NODE *Mem32Bridge;
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PCI_RESOURCE_NODE *PMem32Bridge;
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PCI_RESOURCE_NODE *Mem64Bridge;
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PCI_RESOURCE_NODE *PMem64Bridge;
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PCI_RESOURCE_NODE IoPool;
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PCI_RESOURCE_NODE Mem32Pool;
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PCI_RESOURCE_NODE PMem32Pool;
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PCI_RESOURCE_NODE Mem64Pool;
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PCI_RESOURCE_NODE PMem64Pool;
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REPORT_STATUS_CODE_LIBRARY_DEVICE_HANDLE_EXTENDED_DATA ExtendedData;
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//
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// Initialize resource pool
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//
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InitializeResourcePool (&IoPool, PciBarTypeIo16);
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InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);
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InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);
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InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);
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InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);
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RootBridgeDev = NULL;
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RootBridgeHandle = 0;
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while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
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//
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// Get RootBridg Device by handle
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//
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RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
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if (RootBridgeDev == NULL) {
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return EFI_NOT_FOUND;
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}
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//
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// Get host bridge handle for status report
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//
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ExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
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//
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// Create the entire system resource map from the information collected by
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// enumerator. Several resource tree was created
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//
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IoBridge = CreateResourceNode (
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RootBridgeDev,
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0,
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0xFFF,
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0,
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PciBarTypeIo16,
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PciResUsageTypical
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);
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Mem32Bridge = CreateResourceNode (
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RootBridgeDev,
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0,
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0xFFFFF,
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0,
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PciBarTypeMem32,
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PciResUsageTypical
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);
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PMem32Bridge = CreateResourceNode (
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RootBridgeDev,
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0,
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0xFFFFF,
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0,
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PciBarTypePMem32,
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PciResUsageTypical
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);
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Mem64Bridge = CreateResourceNode (
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RootBridgeDev,
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0,
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0xFFFFF,
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0,
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PciBarTypeMem64,
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PciResUsageTypical
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);
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PMem64Bridge = CreateResourceNode (
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RootBridgeDev,
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0,
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0xFFFFF,
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0,
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PciBarTypePMem64,
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PciResUsageTypical
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);
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//
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// Create resourcemap by going through all the devices subject to this root bridge
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//
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Status = CreateResourceMap (
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RootBridgeDev,
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IoBridge,
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Mem32Bridge,
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PMem32Bridge,
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Mem64Bridge,
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PMem64Bridge
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);
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//
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// Get the max ROM size that the root bridge can process
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//
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RootBridgeDev->RomSize = Mem32Bridge->Length;
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//
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// Get Max Option Rom size for current root bridge
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//
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MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);
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//
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// Enlarger the mem32 resource to accomdate the option rom
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// if the mem32 resource is not enough to hold the rom
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//
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if (MaxOptionRomSize > Mem32Bridge->Length) {
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Mem32Bridge->Length = MaxOptionRomSize;
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RootBridgeDev->RomSize = MaxOptionRomSize;
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//
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// Alignment should be adjusted as well
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//
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if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {
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Mem32Bridge->Alignment = MaxOptionRomSize - 1;
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}
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}
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//
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// Based on the all the resource tree, contruct ACPI resource node to
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// submit the resource aperture to pci host bridge protocol
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//
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Status = ConstructAcpiResourceRequestor (
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RootBridgeDev,
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IoBridge,
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Mem32Bridge,
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PMem32Bridge,
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Mem64Bridge,
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PMem64Bridge,
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&AcpiConfig
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);
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//
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// Insert these resource nodes into the database
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//
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InsertResourceNode (&IoPool, IoBridge);
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InsertResourceNode (&Mem32Pool, Mem32Bridge);
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InsertResourceNode (&PMem32Pool, PMem32Bridge);
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InsertResourceNode (&Mem64Pool, Mem64Bridge);
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InsertResourceNode (&PMem64Pool, PMem64Bridge);
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if (Status == EFI_SUCCESS) {
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//
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// Submit the resource requirement
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//
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Status = PciResAlloc->SubmitResources (
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PciResAlloc,
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RootBridgeDev->Handle,
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AcpiConfig
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);
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}
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//
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// Free acpi resource node
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//
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if (AcpiConfig) {
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gBS->FreePool (AcpiConfig);
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}
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if (EFI_ERROR (Status)) {
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//
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// Destroy all the resource tree
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//
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DestroyResourceTree (&IoPool);
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DestroyResourceTree (&Mem32Pool);
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DestroyResourceTree (&PMem32Pool);
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DestroyResourceTree (&Mem64Pool);
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DestroyResourceTree (&PMem64Pool);
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return Status;
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}
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}
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//
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// End while
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//
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//
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// Notify pci bus driver starts to program the resource
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//
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Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);
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if (EFI_ERROR (Status)) {
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//
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// Allocation failed, then return
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//
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Raise the EFI_IOB_PCI_RES_ALLOC status code
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//
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REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
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EFI_PROGRESS_CODE,
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EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,
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(VOID *) &ExtendedData,
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sizeof (ExtendedData)
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);
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//
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// Notify pci bus driver starts to program the resource
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//
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NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);
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RootBridgeDev = NULL;
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RootBridgeHandle = 0;
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while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
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//
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// Get RootBridg Device by handle
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//
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RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
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if (RootBridgeDev == NULL) {
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return EFI_NOT_FOUND;
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}
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//
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// Get acpi resource node for all the resource types
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//
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AcpiConfig = NULL;
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Status = PciResAlloc->GetProposedResources (
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PciResAlloc,
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RootBridgeDev->Handle,
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&AcpiConfig
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Get the resource base by interpreting acpi resource node
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//
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//
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GetResourceBase (
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AcpiConfig,
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&IoBase,
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&Mem32Base,
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&PMem32Base,
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&Mem64Base,
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&PMem64Base
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);
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//
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// Process option rom for this root bridge
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//
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Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);
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//
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// Create the entire system resource map from the information collected by
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// enumerator. Several resource tree was created
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//
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Status = GetResourceMap (
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RootBridgeDev,
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&IoBridge,
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&Mem32Bridge,
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&PMem32Bridge,
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&Mem64Bridge,
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&PMem64Bridge,
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&IoPool,
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&Mem32Pool,
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&PMem32Pool,
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&Mem64Pool,
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&PMem64Pool
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Program IO resources
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//
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ProgramResource (
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IoBase,
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IoBridge
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);
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//
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// Program Mem32 resources
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//
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ProgramResource (
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Mem32Base,
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Mem32Bridge
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);
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//
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// Program PMem32 resources
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//
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ProgramResource (
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PMem32Base,
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PMem32Bridge
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);
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//
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// Program Mem64 resources
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//
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ProgramResource (
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Mem64Base,
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Mem64Bridge
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);
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//
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// Program PMem64 resources
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//
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ProgramResource (
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PMem64Base,
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PMem64Bridge
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);
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if (AcpiConfig != NULL) {
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gBS->FreePool (AcpiConfig);
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}
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}
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//
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// Destroy all the resource tree
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//
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DestroyResourceTree (&IoPool);
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DestroyResourceTree (&Mem32Pool);
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DestroyResourceTree (&PMem32Pool);
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DestroyResourceTree (&Mem64Pool);
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DestroyResourceTree (&PMem64Pool);
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//
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// Notify the resource allocation phase is to end
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//
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NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PciScanBus (
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IN PCI_IO_DEVICE *Bridge,
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IN UINT8 StartBusNumber,
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OUT UINT8 *SubBusNumber,
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OUT UINT8 *PaddedBusRange
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)
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/*++
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Routine Description:
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This routine is used to assign bus number to the given PCI bus system
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Arguments:
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Returns:
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None
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--*/
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// TODO: Bridge - add argument and description to function comment
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// TODO: StartBusNumber - add argument and description to function comment
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// TODO: SubBusNumber - add argument and description to function comment
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// TODO: PaddedBusRange - add argument and description to function comment
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// TODO: EFI_DEVICE_ERROR - add return value to function comment
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// TODO: EFI_SUCCESS - add return value to function comment
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{
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EFI_STATUS Status;
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PCI_TYPE00 Pci;
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UINT8 Device;
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UINT8 Func;
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UINT64 Address;
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UINTN SecondBus;
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UINT16 Register;
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PCI_IO_DEVICE *PciDevice;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
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PciRootBridgeIo = Bridge->PciRootBridgeIo;
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SecondBus = 0;
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Register = 0;
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ResetAllPpbBusReg (Bridge, StartBusNumber);
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for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
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for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
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//
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// Check to see whether a pci device is present
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//
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Status = PciDevicePresent (
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PciRootBridgeIo,
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&Pci,
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StartBusNumber,
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Device,
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Func
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);
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if (!EFI_ERROR (Status) &&
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(IS_PCI_BRIDGE (&Pci) ||
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IS_CARDBUS_BRIDGE (&Pci))) {
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//
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// Get the bridge information
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//
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Status = PciSearchDevice (
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Bridge,
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&Pci,
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StartBusNumber,
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Device,
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Func,
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&PciDevice
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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(*SubBusNumber)++;
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SecondBus = (*SubBusNumber);
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Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
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Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
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Status = PciRootBridgeIo->Pci.Write (
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PciRootBridgeIo,
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EfiPciWidthUint16,
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Address,
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1,
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&Register
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);
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//
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// Initialize SubBusNumber to SecondBus
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//
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Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
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Status = PciRootBridgeIo->Pci.Write (
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PciRootBridgeIo,
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EfiPciWidthUint8,
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Address,
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1,
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SubBusNumber
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);
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//
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// If it is PPB, resursively search down this bridge
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//
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if (IS_PCI_BRIDGE (&Pci)) {
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//
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// Temporarily initialize SubBusNumber to maximum bus number to ensure the
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// PCI configuration transaction to go through any PPB
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//
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Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
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Register = 0xFF;
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Status = PciRootBridgeIo->Pci.Write (
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PciRootBridgeIo,
|
|
EfiPciWidthUint8,
|
|
Address,
|
|
1,
|
|
&Register
|
|
);
|
|
|
|
PreprocessController (
|
|
PciDevice,
|
|
PciDevice->BusNumber,
|
|
PciDevice->DeviceNumber,
|
|
PciDevice->FunctionNumber,
|
|
EfiPciBeforeChildBusEnumeration
|
|
);
|
|
|
|
Status = PciScanBus (
|
|
PciDevice,
|
|
(UINT8) (SecondBus),
|
|
SubBusNumber,
|
|
PaddedBusRange
|
|
);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return EFI_DEVICE_ERROR;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Set the current maximum bus number under the PPB
|
|
//
|
|
|
|
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
|
|
|
|
Status = PciRootBridgeIo->Pci.Write (
|
|
PciRootBridgeIo,
|
|
EfiPciWidthUint8,
|
|
Address,
|
|
1,
|
|
SubBusNumber
|
|
);
|
|
|
|
}
|
|
|
|
if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
|
|
|
|
//
|
|
// Skip sub functions, this is not a multi function device
|
|
//
|
|
|
|
Func = PCI_MAX_FUNC;
|
|
}
|
|
}
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Light PCI bus driver woundn't support P2C
|
|
// Return instead
|
|
//
|
|
EFI_STATUS
|
|
PciHostBridgeP2CProcess (
|
|
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Arguments:
|
|
|
|
Returns:
|
|
|
|
None
|
|
|
|
--*/
|
|
// TODO: PciResAlloc - add argument and description to function comment
|
|
// TODO: EFI_SUCCESS - add return value to function comment
|
|
{
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Light PCI bus driver woundn't support hotplug device
|
|
// Simplified the code
|
|
//
|
|
EFI_STATUS
|
|
PciHostBridgeEnumerator (
|
|
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is used to enumerate the entire host bridge
|
|
in a given platform
|
|
|
|
Arguments:
|
|
|
|
PciResAlloc A pointer to the protocol to allocate resource.
|
|
|
|
Returns:
|
|
|
|
None
|
|
|
|
--*/
|
|
// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
|
|
// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
|
|
// TODO: EFI_SUCCESS - add return value to function comment
|
|
{
|
|
EFI_HANDLE RootBridgeHandle;
|
|
PCI_IO_DEVICE *RootBridgeDev;
|
|
EFI_STATUS Status;
|
|
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
|
|
UINT16 MinBus;
|
|
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
|
|
|
|
InitializeHotPlugSupport ();
|
|
|
|
//
|
|
// Notify the bus allocation phase is about to start
|
|
//
|
|
NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
|
|
|
|
RootBridgeHandle = NULL;
|
|
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
|
|
|
|
//
|
|
// if a root bridge instance is found, create root bridge device for it
|
|
//
|
|
|
|
RootBridgeDev = CreateRootBridge (RootBridgeHandle);
|
|
|
|
if (RootBridgeDev == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// Enumerate all the buses under this root bridge
|
|
//
|
|
|
|
Status = PciRootBridgeEnumerator (
|
|
PciResAlloc,
|
|
RootBridgeDev
|
|
);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
|
|
DestroyRootBridge (RootBridgeDev);
|
|
|
|
//
|
|
// Error proccess here
|
|
//
|
|
}
|
|
|
|
//
|
|
// Notify the bus allocation phase is to end
|
|
//
|
|
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
|
|
|
|
//
|
|
// Notify the resource allocation phase is to start
|
|
//
|
|
NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);
|
|
|
|
RootBridgeHandle = NULL;
|
|
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
|
|
|
|
//
|
|
// if a root bridge instance is found, create root bridge device for it
|
|
//
|
|
|
|
RootBridgeDev = CreateRootBridge (RootBridgeHandle);
|
|
|
|
if (RootBridgeDev == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
Status = StartManagingRootBridge (RootBridgeDev);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
|
|
PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;
|
|
Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
|
|
Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
|
|
//
|
|
// Determine root bridge attribute by calling interface of Pcihostbridge
|
|
// protocol
|
|
//
|
|
DetermineRootBridgeAttributes (
|
|
PciResAlloc,
|
|
RootBridgeDev
|
|
);
|
|
|
|
//
|
|
// Collect all the resource information under this root bridge
|
|
// A database that records all the information about pci device subject to this
|
|
// root bridge will then be created
|
|
//
|
|
Status = PciPciDeviceInfoCollector (
|
|
RootBridgeDev,
|
|
(UINT8) MinBus
|
|
);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
|
|
InsertRootBridge (RootBridgeDev);
|
|
|
|
//
|
|
// Record the hostbridge handle
|
|
//
|
|
AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|