mirror of https://github.com/acidanthera/audk.git
bfc87aa78e
Today's PiSmmIpl implementation initially sets SMRAM to WB to speed up the SMM core/modules loading before SMM CPU driver runs. When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done in SmmIplDxeDispatchEventNotify(). COMM_BUFFER_SMM_DISPATCH_RESTART is returned from SMM core that SMM CPU driver is just dispatched. Since now the SMRR is widely used to control the SMRAM cache setting. It's not needed to reset the SMRAM to UC anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> |
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| .. | ||
| Dxe | ||
| DxeIplPeim | ||
| Pei | ||
| PiSmmCore | ||
| RuntimeDxe | ||