mirror of https://github.com/acidanthera/audk.git
526 lines
16 KiB
C
526 lines
16 KiB
C
/** @file
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Read EDID information and parse EDID information.
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Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CirrusLogic5430.h"
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#include "CirrusLogic5430I2c.h"
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//
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// EDID block
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//
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typedef struct {
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UINT8 Header[8]; //EDID header "00 FF FF FF FF FF FF 00"
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UINT16 ManufactureName; //EISA 3-character ID
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UINT16 ProductCode; //Vendor assigned code
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UINT32 SerialNumber; //32-bit serial number
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UINT8 WeekOfManufacture; //Week number
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UINT8 YearOfManufacture; //Year
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UINT8 EdidVersion; //EDID Structure Version
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UINT8 EdidRevision; //EDID Structure Revision
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UINT8 VideoInputDefinition;
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UINT8 MaxHorizontalImageSize; //cm
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UINT8 MaxVerticalImageSize; //cm
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UINT8 DisplayTransferCharacteristic;
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UINT8 FeatureSupport;
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UINT8 RedGreenLowBits; //Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1Gy0
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UINT8 BlueWhiteLowBits; //Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0
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UINT8 RedX; //Red-x Bits 9 - 2
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UINT8 RedY; //Red-y Bits 9 - 2
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UINT8 GreenX; //Green-x Bits 9 - 2
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UINT8 GreenY; //Green-y Bits 9 - 2
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UINT8 BlueX; //Blue-x Bits 9 - 2
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UINT8 BlueY; //Blue-y Bits 9 - 2
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UINT8 WhiteX; //White-x Bits 9 - 2
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UINT8 WhiteY; //White-x Bits 9 - 2
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UINT8 EstablishedTimings[3];
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UINT8 StandardTimingIdentification[16];
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UINT8 DetailedTimingDescriptions[72];
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UINT8 ExtensionFlag; //Number of (optional) 128-byte EDID extension blocks to follow
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UINT8 Checksum;
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} EDID_BLOCK;
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#define EDID_BLOCK_SIZE 128
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#define VBE_EDID_ESTABLISHED_TIMING_MAX_NUMBER 17
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typedef struct {
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UINT16 HorizontalResolution;
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UINT16 VerticalResolution;
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UINT16 RefreshRate;
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} EDID_TIMING;
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typedef struct {
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UINT32 ValidNumber;
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UINT32 Key[VBE_EDID_ESTABLISHED_TIMING_MAX_NUMBER];
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} VALID_EDID_TIMING;
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//
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// Standard timing defined by VESA EDID
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//
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EDID_TIMING mVbeEstablishedEdidTiming[] = {
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//
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// Established Timing I
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//
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{800, 600, 60},
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{800, 600, 56},
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{640, 480, 75},
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{640, 480, 72},
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{640, 480, 67},
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{640, 480, 60},
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{720, 400, 88},
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{720, 400, 70},
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//
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// Established Timing II
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//
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{1280, 1024, 75},
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{1024, 768, 75},
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{1024, 768, 70},
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{1024, 768, 60},
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{1024, 768, 87},
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{832, 624, 75},
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{800, 600, 75},
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{800, 600, 72},
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//
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// Established Timing III
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//
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{1152, 870, 75}
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};
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/**
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Read EDID information from I2C Bus on CirrusLogic.
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@param Private Pointer to CIRRUS_LOGIC_5430_PRIVATE_DATA.
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@param EdidDataBlock Pointer to EDID data block.
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@param EdidSize Returned EDID block size.
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@retval EFI_UNSUPPORTED
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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ReadEdidData (
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CIRRUS_LOGIC_5430_PRIVATE_DATA *Private,
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UINT8 **EdidDataBlock,
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UINTN *EdidSize
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)
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{
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UINTN Index;
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UINT8 EdidData[EDID_BLOCK_SIZE * 2];
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UINT8 *ValidEdid;
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UINT64 Signature;
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for (Index = 0; Index < EDID_BLOCK_SIZE * 2; Index ++) {
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I2cReadByte (Private->PciIo, 0xa0, (UINT8)Index, &EdidData[Index]);
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}
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//
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// Search for the EDID signature
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//
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ValidEdid = &EdidData[0];
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Signature = 0x00ffffffffffff00ull;
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for (Index = 0; Index < EDID_BLOCK_SIZE * 2; Index ++, ValidEdid ++) {
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if (CompareMem (ValidEdid, &Signature, 8) == 0) {
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break;
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}
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}
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if (Index == 256) {
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//
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// No EDID signature found
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//
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return EFI_UNSUPPORTED;
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}
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*EdidDataBlock = AllocateCopyPool (
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EDID_BLOCK_SIZE,
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ValidEdid
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);
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if (*EdidDataBlock == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Currently only support EDID 1.x
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//
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*EdidSize = EDID_BLOCK_SIZE;
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return EFI_SUCCESS;
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}
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/**
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Generate a search key for a specified timing data.
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@param EdidTiming Pointer to EDID timing
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@return The 32 bit unique key for search.
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**/
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UINT32
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CalculateEdidKey (
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EDID_TIMING *EdidTiming
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)
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{
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UINT32 Key;
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//
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// Be sure no conflicts for all standard timing defined by VESA.
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//
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Key = (EdidTiming->HorizontalResolution * 2) + EdidTiming->VerticalResolution;
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return Key;
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}
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/**
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Search a specified Timing in all the valid EDID timings.
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@param ValidEdidTiming All valid EDID timing information.
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@param EdidTiming The Timing to search for.
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@retval TRUE Found.
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@retval FALSE Not found.
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**/
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BOOLEAN
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SearchEdidTiming (
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VALID_EDID_TIMING *ValidEdidTiming,
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EDID_TIMING *EdidTiming
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)
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{
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UINT32 Index;
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UINT32 Key;
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Key = CalculateEdidKey (EdidTiming);
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for (Index = 0; Index < ValidEdidTiming->ValidNumber; Index ++) {
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if (Key == ValidEdidTiming->Key[Index]) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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Parse the Established Timing and Standard Timing in EDID data block.
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@param EdidBuffer Pointer to EDID data block
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@param ValidEdidTiming Valid EDID timing information
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@retval TRUE The EDID data is valid.
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@retval FALSE The EDID data is invalid.
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**/
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BOOLEAN
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ParseEdidData (
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UINT8 *EdidBuffer,
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VALID_EDID_TIMING *ValidEdidTiming
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)
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{
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UINT8 CheckSum;
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UINT32 Index;
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UINT32 ValidNumber;
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UINT32 TimingBits;
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UINT8 *BufferIndex;
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UINT16 HorizontalResolution;
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UINT16 VerticalResolution;
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UINT8 AspectRatio;
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UINT8 RefreshRate;
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EDID_TIMING TempTiming;
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EDID_BLOCK *EdidDataBlock;
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EdidDataBlock = (EDID_BLOCK *) EdidBuffer;
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//
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// Check the checksum of EDID data
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//
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CheckSum = 0;
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for (Index = 0; Index < EDID_BLOCK_SIZE; Index ++) {
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CheckSum = (UINT8) (CheckSum + EdidBuffer[Index]);
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}
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if (CheckSum != 0) {
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return FALSE;
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}
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ValidNumber = 0;
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SetMem (ValidEdidTiming, sizeof (VALID_EDID_TIMING), 0);
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if ((EdidDataBlock->EstablishedTimings[0] != 0) ||
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(EdidDataBlock->EstablishedTimings[1] != 0) ||
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(EdidDataBlock->EstablishedTimings[2] != 0)
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) {
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//
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// Established timing data
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//
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TimingBits = EdidDataBlock->EstablishedTimings[0] |
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(EdidDataBlock->EstablishedTimings[1] << 8) |
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((EdidDataBlock->EstablishedTimings[2] & 0x80) << 9) ;
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for (Index = 0; Index < VBE_EDID_ESTABLISHED_TIMING_MAX_NUMBER; Index ++) {
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if (TimingBits & 0x1) {
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ValidEdidTiming->Key[ValidNumber] = CalculateEdidKey (&mVbeEstablishedEdidTiming[Index]);
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ValidNumber ++;
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}
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TimingBits = TimingBits >> 1;
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}
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} else {
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//
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// If no Established timing data, read the standard timing data
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//
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BufferIndex = &EdidDataBlock->StandardTimingIdentification[0];
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for (Index = 0; Index < 8; Index ++) {
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if ((BufferIndex[0] != 0x1) && (BufferIndex[1] != 0x1)){
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//
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// A valid Standard Timing
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//
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HorizontalResolution = (UINT16) (BufferIndex[0] * 8 + 248);
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AspectRatio = (UINT8) (BufferIndex[1] >> 6);
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switch (AspectRatio) {
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case 0:
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VerticalResolution = (UINT16) (HorizontalResolution / 16 * 10);
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break;
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case 1:
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VerticalResolution = (UINT16) (HorizontalResolution / 4 * 3);
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break;
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case 2:
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VerticalResolution = (UINT16) (HorizontalResolution / 5 * 4);
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break;
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case 3:
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VerticalResolution = (UINT16) (HorizontalResolution / 16 * 9);
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break;
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default:
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VerticalResolution = (UINT16) (HorizontalResolution / 4 * 3);
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break;
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}
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RefreshRate = (UINT8) ((BufferIndex[1] & 0x1f) + 60);
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TempTiming.HorizontalResolution = HorizontalResolution;
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TempTiming.VerticalResolution = VerticalResolution;
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TempTiming.RefreshRate = RefreshRate;
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ValidEdidTiming->Key[ValidNumber] = CalculateEdidKey (&TempTiming);
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ValidNumber ++;
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}
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BufferIndex += 2;
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}
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}
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ValidEdidTiming->ValidNumber = ValidNumber;
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return TRUE;
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}
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/**
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Construct the valid video modes for CirrusLogic5430.
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**/
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EFI_STATUS
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CirrusLogic5430VideoModeSetup (
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CIRRUS_LOGIC_5430_PRIVATE_DATA *Private
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)
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{
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EFI_STATUS Status;
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UINT32 Index;
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BOOLEAN EdidFound;
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EFI_EDID_OVERRIDE_PROTOCOL *EdidOverride;
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UINT32 EdidAttributes;
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BOOLEAN EdidOverrideFound;
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UINTN EdidOverrideDataSize;
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UINT8 *EdidOverrideDataBlock;
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UINTN EdidDiscoveredDataSize;
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UINT8 *EdidDiscoveredDataBlock;
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UINTN EdidActiveDataSize;
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UINT8 *EdidActiveDataBlock;
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VALID_EDID_TIMING ValidEdidTiming;
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UINT32 ValidModeCount;
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CIRRUS_LOGIC_5430_MODE_DATA *ModeData;
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BOOLEAN TimingMatch;
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CIRRUS_LOGIC_5430_VIDEO_MODES *VideoMode;
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EDID_TIMING TempTiming;
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//
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// setup EDID information
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//
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Private->EdidDiscovered.Edid = NULL;
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Private->EdidDiscovered.SizeOfEdid = 0;
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Private->EdidActive.Edid = NULL;
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Private->EdidActive.SizeOfEdid = 0;
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EdidFound = FALSE;
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EdidOverrideFound = FALSE;
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EdidAttributes = 0xff;
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EdidOverrideDataSize = 0;
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EdidOverrideDataBlock = NULL;
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EdidActiveDataSize = 0;
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EdidActiveDataBlock = NULL;
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EdidDiscoveredDataBlock = NULL;
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//
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// Find EDID Override protocol firstly, this protocol is installed by platform if needed.
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//
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Status = gBS->LocateProtocol (
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&gEfiEdidOverrideProtocolGuid,
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NULL,
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(VOID **) &EdidOverride
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);
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if (!EFI_ERROR (Status)) {
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//
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// Allocate double size of VESA_BIOS_EXTENSIONS_EDID_BLOCK_SIZE to avoid overflow
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//
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EdidOverrideDataBlock = AllocatePool (EDID_BLOCK_SIZE * 2);
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if (NULL == EdidOverrideDataBlock) {
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Status = EFI_OUT_OF_RESOURCES;
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goto Done;
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}
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Status = EdidOverride->GetEdid (
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EdidOverride,
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Private->Handle,
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&EdidAttributes,
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&EdidOverrideDataSize,
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(UINT8 **) &EdidOverrideDataBlock
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);
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if (!EFI_ERROR (Status) &&
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EdidAttributes == 0 &&
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EdidOverrideDataSize != 0) {
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//
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// Succeeded to get EDID Override Data
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//
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EdidOverrideFound = TRUE;
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}
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}
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if (EdidOverrideFound != TRUE || EdidAttributes == EFI_EDID_OVERRIDE_DONT_OVERRIDE) {
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//
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// If EDID Override data doesn't exist or EFI_EDID_OVERRIDE_DONT_OVERRIDE returned,
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// read EDID information through I2C Bus
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//
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if (ReadEdidData (Private, &EdidDiscoveredDataBlock, &EdidDiscoveredDataSize) == EFI_SUCCESS) {
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Private->EdidDiscovered.SizeOfEdid = (UINT32) EdidDiscoveredDataSize;
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Private->EdidDiscovered.Edid = (UINT8 *) AllocateCopyPool (
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EdidDiscoveredDataSize,
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EdidDiscoveredDataBlock
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);
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if (NULL == Private->EdidDiscovered.Edid) {
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Status = EFI_OUT_OF_RESOURCES;
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goto Done;
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}
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EdidActiveDataSize = Private->EdidDiscovered.SizeOfEdid;
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EdidActiveDataBlock = Private->EdidDiscovered.Edid;
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EdidFound = TRUE;
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}
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}
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if (EdidFound != TRUE && EdidOverrideFound == TRUE) {
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EdidActiveDataSize = EdidOverrideDataSize;
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EdidActiveDataBlock = EdidOverrideDataBlock;
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EdidFound = TRUE;
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}
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if (EdidFound == TRUE) {
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//
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// Parse EDID data structure to retrieve modes supported by monitor
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//
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if (ParseEdidData ((UINT8 *) EdidActiveDataBlock, &ValidEdidTiming) == TRUE) {
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//
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// Copy EDID Override Data to EDID Active Data
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//
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Private->EdidActive.SizeOfEdid = (UINT32) EdidActiveDataSize;
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Private->EdidActive.Edid = (UINT8 *) AllocateCopyPool (
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EdidActiveDataSize,
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EdidActiveDataBlock
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);
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if (NULL == Private->EdidActive.Edid) {
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Status = EFI_OUT_OF_RESOURCES;
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goto Done;
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}
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}
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} else {
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Private->EdidActive.SizeOfEdid = 0;
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Private->EdidActive.Edid = NULL;
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EdidFound = FALSE;
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}
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if (EdidFound) {
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//
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// Initialize the private mode data with the supported modes.
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//
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ValidModeCount = 0;
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ModeData = &Private->ModeData[0];
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VideoMode = &CirrusLogic5430VideoModes[0];
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for (Index = 0; Index < CIRRUS_LOGIC_5430_MODE_COUNT; Index++) {
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TimingMatch = TRUE;
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//
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// Check whether match with CirrusLogic5430 video mode
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//
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TempTiming.HorizontalResolution = (UINT16) VideoMode->Width;
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TempTiming.VerticalResolution = (UINT16) VideoMode->Height;
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TempTiming.RefreshRate = (UINT16) VideoMode->RefreshRate;
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if (SearchEdidTiming (&ValidEdidTiming, &TempTiming) != TRUE) {
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TimingMatch = FALSE;
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}
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//
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// Not export Mode 0x0 as GOP mode, this is not defined in spec.
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//
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if ((VideoMode->Width == 0) || (VideoMode->Height == 0)) {
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TimingMatch = FALSE;
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}
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if (TimingMatch) {
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ModeData->ModeNumber = Index;
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ModeData->HorizontalResolution = VideoMode->Width;
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ModeData->VerticalResolution = VideoMode->Height;
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ModeData->ColorDepth = VideoMode->ColorDepth;
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ModeData->RefreshRate = VideoMode->RefreshRate;
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ModeData ++;
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ValidModeCount ++;
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}
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VideoMode ++;
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}
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Private->MaxMode = ValidModeCount;
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} else {
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//
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// If EDID information wasn't found
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//
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ModeData = &Private->ModeData[0];
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VideoMode = &CirrusLogic5430VideoModes[0];
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for (Index = 0; Index < CIRRUS_LOGIC_5430_MODE_COUNT; Index ++) {
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ModeData->ModeNumber = Index;
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ModeData->HorizontalResolution = VideoMode->Width;
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ModeData->VerticalResolution = VideoMode->Height;
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ModeData->ColorDepth = VideoMode->ColorDepth;
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ModeData->RefreshRate = VideoMode->RefreshRate;
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ModeData ++ ;
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VideoMode ++;
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}
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Private->MaxMode = CIRRUS_LOGIC_5430_MODE_COUNT;
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}
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if (EdidOverrideDataBlock != NULL) {
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FreePool (EdidOverrideDataBlock);
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}
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return EFI_SUCCESS;
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Done:
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if (EdidOverrideDataBlock != NULL) {
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FreePool (EdidOverrideDataBlock);
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}
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if (Private->EdidDiscovered.Edid != NULL) {
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FreePool (Private->EdidDiscovered.Edid);
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}
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if (Private->EdidDiscovered.Edid != NULL) {
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FreePool (Private->EdidActive.Edid);
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}
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return EFI_DEVICE_ERROR;
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}
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