mirror of https://github.com/acidanthera/audk.git
551 lines
19 KiB
C
551 lines
19 KiB
C
/** @file
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Support for PCI 2.2 standard.
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Copyright (c) 2006 - 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name: pci22.h
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**/
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#ifndef _PCI22_H
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#define _PCI22_H
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#define PCI_MAX_SEGMENT 0
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#define PCI_MAX_BUS 255
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#define PCI_MAX_DEVICE 31
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#define PCI_MAX_FUNC 7
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//
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// Command
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//
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#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
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#pragma pack(push, 1)
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typedef struct {
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Command;
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UINT16 Status;
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UINT8 RevisionID;
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UINT8 ClassCode[3];
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UINT8 CacheLineSize;
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UINT8 LatencyTimer;
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UINT8 HeaderType;
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UINT8 BIST;
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} PCI_DEVICE_INDEPENDENT_REGION;
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typedef struct {
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UINT32 Bar[6];
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UINT32 CISPtr;
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UINT16 SubsystemVendorID;
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UINT16 SubsystemID;
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UINT32 ExpansionRomBar;
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UINT8 CapabilityPtr;
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UINT8 Reserved1[3];
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UINT32 Reserved2;
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UINT8 InterruptLine;
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UINT8 InterruptPin;
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UINT8 MinGnt;
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UINT8 MaxLat;
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} PCI_DEVICE_HEADER_TYPE_REGION;
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typedef struct {
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_DEVICE_HEADER_TYPE_REGION Device;
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} PCI_TYPE00;
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typedef struct {
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UINT32 Bar[2];
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UINT8 PrimaryBus;
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UINT8 SecondaryBus;
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UINT8 SubordinateBus;
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UINT8 SecondaryLatencyTimer;
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UINT8 IoBase;
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UINT8 IoLimit;
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UINT16 SecondaryStatus;
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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UINT16 PrefetchableMemoryBase;
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UINT16 PrefetchableMemoryLimit;
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UINT32 PrefetchableBaseUpper32;
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UINT32 PrefetchableLimitUpper32;
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UINT16 IoBaseUpper16;
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UINT16 IoLimitUpper16;
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UINT8 CapabilityPtr;
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UINT8 Reserved[3];
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UINT32 ExpansionRomBAR;
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UINT8 InterruptLine;
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UINT8 InterruptPin;
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UINT16 BridgeControl;
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} PCI_BRIDGE_CONTROL_REGISTER;
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typedef struct {
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_BRIDGE_CONTROL_REGISTER Bridge;
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} PCI_TYPE01;
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typedef union {
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PCI_TYPE00 Device;
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PCI_TYPE01 Bridge;
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} PCI_TYPE_GENERIC;
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typedef struct {
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UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
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// Address Register
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//
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UINT16 Reserved;
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UINT16 SecondaryStatus; // Secondary Status
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UINT8 PciBusNumber; // PCI Bus Number
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UINT8 CardBusBusNumber; // CardBus Bus Number
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UINT8 SubordinateBusNumber; // Subordinate Bus Number
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UINT8 CardBusLatencyTimer; // CardBus Latency Timer
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UINT32 MemoryBase0; // Memory Base Register 0
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UINT32 MemoryLimit0; // Memory Limit Register 0
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UINT32 MemoryBase1;
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UINT32 MemoryLimit1;
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UINT32 IoBase0;
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UINT32 IoLimit0; // I/O Base Register 0
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UINT32 IoBase1; // I/O Limit Register 0
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UINT32 IoLimit1;
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UINT8 InterruptLine; // Interrupt Line
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UINT8 InterruptPin; // Interrupt Pin
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UINT16 BridgeControl; // Bridge Control
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} PCI_CARDBUS_CONTROL_REGISTER;
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//
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// Definitions of PCI class bytes and manipulation macros.
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//
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#define PCI_CLASS_OLD 0x00
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#define PCI_CLASS_OLD_OTHER 0x00
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#define PCI_CLASS_OLD_VGA 0x01
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
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#define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
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#define PCI_CLASS_IDE 0x01
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#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_CLASS_MASS_STORAGE_IPI 0x03
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#define PCI_CLASS_MASS_STORAGE_RAID 0x04
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#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x00
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#define PCI_CLASS_ETHERNET 0x00 // obsolete
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#define PCI_CLASS_NETWORK_TOKENRING 0x01
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#define PCI_CLASS_NETWORK_FDDI 0x02
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#define PCI_CLASS_NETWORK_ATM 0x03
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#define PCI_CLASS_NETWORK_ISDN 0x04
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#define PCI_CLASS_NETWORK_OTHER 0x80
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#define PCI_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
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#define PCI_CLASS_DISPLAY_VGA 0x00
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#define PCI_CLASS_VGA 0x00 // obsolete
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#define PCI_CLASS_DISPLAY_XGA 0x01
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#define PCI_CLASS_DISPLAY_3D 0x02
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#define PCI_CLASS_DISPLAY_OTHER 0x80
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#define PCI_CLASS_DISPLAY_GFX 0x80
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#define PCI_CLASS_GFX 0x80 // obsolete
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x00
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#define PCI_CLASS_BRIDGE_ISA 0x01
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#define PCI_CLASS_ISA 0x01 // obsolete
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#define PCI_CLASS_BRIDGE_EISA 0x02
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#define PCI_CLASS_BRIDGE_MCA 0x03
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#define PCI_CLASS_BRIDGE_P2P 0x04
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#define PCI_CLASS_BRIDGE_PCMCIA 0x05
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#define PCI_CLASS_BRIDGE_NUBUS 0x06
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#define PCI_CLASS_BRIDGE_CARDBUS 0x07
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#define PCI_CLASS_BRIDGE_RACEWAY 0x08
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#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
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#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
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#define PCI_CLASS_SCC 0x07 // Simple communications controllers
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#define PCI_SUBCLASS_SERIAL 0x00
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#define PCI_IF_GENERIC_XT 0x00
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#define PCI_IF_16450 0x01
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#define PCI_IF_16550 0x02
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#define PCI_IF_16650 0x03
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#define PCI_IF_16750 0x04
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#define PCI_IF_16850 0x05
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#define PCI_IF_16950 0x06
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#define PCI_SUBCLASS_PARALLEL 0x01
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#define PCI_IF_PARALLEL_PORT 0x00
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#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
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#define PCI_IF_ECP_PARALLEL_PORT 0x02
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#define PCI_IF_1284_CONTROLLER 0x03
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#define PCI_IF_1284_DEVICE 0xFE
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#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
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#define PCI_SUBCLASS_MODEM 0x03
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#define PCI_IF_GENERIC_MODEM 0x00
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#define PCI_IF_16450_MODEM 0x01
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#define PCI_IF_16550_MODEM 0x02
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#define PCI_IF_16650_MODEM 0x03
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#define PCI_IF_16750_MODEM 0x04
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#define PCI_SUBCLASS_OTHER 0x80
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#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
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#define PCI_SUBCLASS_PIC 0x00
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#define PCI_IF_8259_PIC 0x00
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#define PCI_IF_ISA_PIC 0x01
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#define PCI_IF_EISA_PIC 0x02
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#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
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#define PCI_IF_APIC_CONTROLLER2 0x20
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#define PCI_SUBCLASS_TIMER 0x02
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#define PCI_IF_8254_TIMER 0x00
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#define PCI_IF_ISA_TIMER 0x01
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#define PCI_EISA_TIMER 0x02
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#define PCI_SUBCLASS_RTC 0x03
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#define PCI_IF_GENERIC_RTC 0x00
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#define PCI_IF_ISA_RTC 0x00
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#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
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#define PCI_CLASS_INPUT_DEVICE 0x09
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#define PCI_SUBCLASS_KEYBOARD 0x00
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#define PCI_SUBCLASS_PEN 0x01
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#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
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#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
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#define PCI_SUBCLASS_GAMEPORT 0x04
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#define PCI_CLASS_DOCKING_STATION 0x0A
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#define PCI_CLASS_PROCESSOR 0x0B
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#define PCI_SUBCLASS_PROC_386 0x00
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#define PCI_SUBCLASS_PROC_486 0x01
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#define PCI_SUBCLASS_PROC_PENTIUM 0x02
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#define PCI_SUBCLASS_PROC_ALPHA 0x10
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#define PCI_SUBCLASS_PROC_POWERPC 0x20
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#define PCI_SUBCLASS_PROC_MIPS 0x30
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#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
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#define PCI_CLASS_SERIAL 0x0C
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#define PCI_CLASS_SERIAL_FIREWIRE 0x00
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#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
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#define PCI_CLASS_SERIAL_SSA 0x02
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#define PCI_CLASS_SERIAL_USB 0x03
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#define PCI_IF_EHCI 0x20
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#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
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#define PCI_CLASS_SERIAL_SMB 0x05
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#define PCI_CLASS_WIRELESS 0x0D
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#define PCI_SUBCLASS_IRDA 0x00
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#define PCI_SUBCLASS_IR 0x01
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#define PCI_SUBCLASS_RF 0x02
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#define PCI_CLASS_INTELLIGENT_IO 0x0E
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#define PCI_CLASS_SATELLITE 0x0F
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#define PCI_SUBCLASS_TV 0x01
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#define PCI_SUBCLASS_AUDIO 0x02
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#define PCI_SUBCLASS_VOICE 0x03
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#define PCI_SUBCLASS_DATA 0x04
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#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
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#define PCI_SUBCLASS_NET_COMPUT 0x00
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#define PCI_SUBCLASS_ENTERTAINMENT 0x10
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#define PCI_CLASS_DPIO 0x11
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#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
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#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
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#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
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#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
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#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
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#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
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#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
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#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
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#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
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#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
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#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
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#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
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#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
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#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
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#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
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#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
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#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
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#define HEADER_TYPE_DEVICE 0x00
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#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
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#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
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#define HEADER_TYPE_MULTI_FUNCTION 0x80
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#define HEADER_LAYOUT_CODE 0x7f
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#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
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#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
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#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
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#define PCI_DEVICE_ROMBAR 0x30
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#define PCI_BRIDGE_ROMBAR 0x38
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#define PCI_MAX_BAR 0x0006
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#define PCI_MAX_CONFIG_OFFSET 0x0100
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#define PCI_VENDOR_ID_OFFSET 0x00
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#define PCI_DEVICE_ID_OFFSET 0x02
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#define PCI_COMMAND_OFFSET 0x04
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#define PCI_PRIMARY_STATUS_OFFSET 0x06
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#define PCI_REVISION_ID_OFFSET 0x08
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#define PCI_CLASSCODE_OFFSET 0x09
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#define PCI_CACHELINE_SIZE_OFFSET 0x0C
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#define PCI_LATENCY_TIMER_OFFSET 0x0D
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#define PCI_HEADER_TYPE_OFFSET 0x0E
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#define PCI_BIST_OFFSET 0x0F
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#define PCI_BASE_ADDRESSREG_OFFSET 0x10
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#define PCI_CARDBUS_CIS_OFFSET 0x28
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#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
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#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
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#define PCI_SID_OFFSET 0x2E // SubSystem ID
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#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
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#define PCI_EXPANSION_ROM_BASE 0x30
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#define PCI_CAPBILITY_POINTER_OFFSET 0x34
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#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
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#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
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#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
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#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
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#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
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#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
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#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
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#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
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#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
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//
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// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
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//
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#define PCI_INT_LINE_UNKNOWN 0xFF
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typedef union {
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struct {
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UINT32 Reg : 8;
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UINT32 Func : 3;
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UINT32 Dev : 5;
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UINT32 Bus : 8;
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UINT32 Reserved : 7;
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UINT32 Enable : 1;
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} Bits;
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UINT32 Uint32;
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} PCI_CONFIG_ACCESS_CF8;
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#pragma pack()
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#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
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#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
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#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
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#define PCI_CODE_TYPE_EFI_IMAGE 0x03
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#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
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#define EFI_PCI_COMMAND_IO_SPACE 0x0001
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#define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
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#define EFI_PCI_COMMAND_BUS_MASTER 0x0004
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#define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
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#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
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#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
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#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
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#define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
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#define EFI_PCI_COMMAND_SERR 0x0100
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#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
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#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
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#define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
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#define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
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#define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
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#define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
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#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
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#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
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#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
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#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
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#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
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#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
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#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
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//
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// Following are the PCI-CARDBUS bridge control bit
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//
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#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
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#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
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#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
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#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
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//
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// Following are the PCI status control bit
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//
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#define EFI_PCI_STATUS_CAPABILITY 0x0010
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#define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
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#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
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#define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
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#define EFI_PCI_CAPABILITY_PTR 0x34
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#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
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#pragma pack(1)
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typedef struct {
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UINT16 Signature; // 0xaa55
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UINT8 Reserved[0x16];
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UINT16 PcirOffset;
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} PCI_EXPANSION_ROM_HEADER;
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typedef struct {
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UINT16 Signature; // 0xaa55
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UINT8 Size512;
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UINT8 InitEntryPoint[3];
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UINT8 Reserved[0x12];
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UINT16 PcirOffset;
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} EFI_LEGACY_EXPANSION_ROM_HEADER;
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typedef struct {
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UINT32 Signature; // "PCIR"
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Reserved0;
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UINT16 Length;
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UINT8 Revision;
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UINT8 ClassCode[3];
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UINT16 ImageLength;
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UINT16 CodeRevision;
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UINT8 CodeType;
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UINT8 Indicator;
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UINT16 Reserved1;
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} PCI_DATA_STRUCTURE;
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//
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// PCI Capability List IDs and records
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//
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#define EFI_PCI_CAPABILITY_ID_PMI 0x01
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#define EFI_PCI_CAPABILITY_ID_AGP 0x02
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#define EFI_PCI_CAPABILITY_ID_VPD 0x03
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#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
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#define EFI_PCI_CAPABILITY_ID_MSI 0x05
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#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
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#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
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typedef struct {
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UINT8 CapabilityID;
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UINT8 NextItemPtr;
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} EFI_PCI_CAPABILITY_HDR;
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//
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// Capability EFI_PCI_CAPABILITY_ID_PMI
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//
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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UINT16 PMC;
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UINT16 PMCSR;
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UINT8 BridgeExtention;
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UINT8 Data;
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} EFI_PCI_CAPABILITY_PMI;
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//
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// Capability EFI_PCI_CAPABILITY_ID_AGP
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//
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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UINT8 Rev;
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UINT8 Reserved;
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UINT32 Status;
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UINT32 Command;
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} EFI_PCI_CAPABILITY_AGP;
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|
|
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//
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// Capability EFI_PCI_CAPABILITY_ID_VPD
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//
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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UINT16 AddrReg;
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UINT32 DataReg;
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} EFI_PCI_CAPABILITY_VPD;
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|
|
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//
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// Capability EFI_PCI_CAPABILITY_ID_SLOTID
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|
//
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typedef struct {
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|
EFI_PCI_CAPABILITY_HDR Hdr;
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UINT8 ExpnsSlotReg;
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UINT8 ChassisNo;
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} EFI_PCI_CAPABILITY_SLOTID;
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|
|
|
//
|
|
// Capability EFI_PCI_CAPABILITY_ID_MSI
|
|
//
|
|
typedef struct {
|
|
EFI_PCI_CAPABILITY_HDR Hdr;
|
|
UINT16 MsgCtrlReg;
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|
UINT32 MsgAddrReg;
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|
UINT16 MsgDataReg;
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|
} EFI_PCI_CAPABILITY_MSI32;
|
|
|
|
typedef struct {
|
|
EFI_PCI_CAPABILITY_HDR Hdr;
|
|
UINT16 MsgCtrlReg;
|
|
UINT32 MsgAddrRegLsdw;
|
|
UINT32 MsgAddrRegMsdw;
|
|
UINT16 MsgDataReg;
|
|
} EFI_PCI_CAPABILITY_MSI64;
|
|
|
|
//
|
|
// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
|
|
//
|
|
typedef struct {
|
|
EFI_PCI_CAPABILITY_HDR Hdr;
|
|
//
|
|
// not finished - fields need to go here
|
|
//
|
|
} EFI_PCI_CAPABILITY_HOTPLUG;
|
|
|
|
//
|
|
// Capability EFI_PCI_CAPABILITY_ID_PCIX
|
|
//
|
|
typedef struct {
|
|
EFI_PCI_CAPABILITY_HDR Hdr;
|
|
UINT16 CommandReg;
|
|
UINT32 StatusReg;
|
|
} EFI_PCI_CAPABILITY_PCIX;
|
|
|
|
typedef struct {
|
|
EFI_PCI_CAPABILITY_HDR Hdr;
|
|
UINT16 SecStatusReg;
|
|
UINT32 StatusReg;
|
|
UINT32 SplitTransCtrlRegUp;
|
|
UINT32 SplitTransCtrlRegDn;
|
|
} EFI_PCI_CAPABILITY_PCIX_BRDG;
|
|
|
|
#define DEVICE_ID_NOCARE 0xFFFF
|
|
|
|
#define PCI_ACPI_UNUSED 0
|
|
#define PCI_BAR_NOCHANGE 0
|
|
#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
|
|
#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
|
|
#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
|
|
#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
|
|
|
|
#define PCI_BAR_IDX0 0x00
|
|
#define PCI_BAR_IDX1 0x01
|
|
#define PCI_BAR_IDX2 0x02
|
|
#define PCI_BAR_IDX3 0x03
|
|
#define PCI_BAR_IDX4 0x04
|
|
#define PCI_BAR_IDX5 0x05
|
|
#define PCI_BAR_ALL 0xFF
|
|
|
|
#pragma pack(pop)
|
|
|
|
//
|
|
// NOTE: The following header files are included here for
|
|
// compatibility consideration.
|
|
//
|
|
#include "pci23.h"
|
|
#include "pci30.h"
|
|
#include "EfiPci.h"
|
|
|
|
#endif
|