mirror of https://github.com/acidanthera/audk.git
518 lines
14 KiB
Plaintext
518 lines
14 KiB
Plaintext
/** @file
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The TPM2 definition block in ACPI table for TCG2 physical presence
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and MemoryClear.
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Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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(c)Copyright 2016 HP Development Company, L.P.<BR>
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Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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DefinitionBlock (
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"Tpm.aml",
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"SSDT",
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2,
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"INTEL ",
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"Tpm2Tabl",
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0x1000
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)
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{
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Scope (\_SB)
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{
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Device (TPM)
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{
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//
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// TCG2
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//
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//
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// TAG for patching TPM2.0 _HID
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//
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Name (_HID, "NNNN0000")
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Name (_CID, "MSFT0101")
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//
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// Readable name of this device, don't know if this way is correct yet
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//
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Name (_STR, Unicode ("TPM 2.0 Device"))
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//
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// Operational region for Smi port access
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//
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OperationRegion (SMIP, SystemIO, 0xB2, 1)
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Field (SMIP, ByteAcc, NoLock, Preserve)
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{
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IOB2, 8
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}
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//
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// Operational region for TPM access
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//
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OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)
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Field (TPMR, AnyAcc, NoLock, Preserve)
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{
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ACC0, 8, // TPM_ACCESS_0
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Offset(0x8),
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INTE, 32, // TPM_INT_ENABLE_0
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INTV, 8, // TPM_INT_VECTOR_0
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Offset(0x10),
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INTS, 32, // TPM_INT_STATUS_0
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INTF, 32, // TPM_INTF_CAPABILITY_0
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STS0, 32, // TPM_STS_0
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Offset(0x24),
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FIFO, 32, // TPM_DATA_FIFO_0
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Offset(0x30),
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TID0, 32, // TPM_INTERFACE_ID_0
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// ignore the rest
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}
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//
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// Operational region for TPM support, TPM Physical Presence and TPM Memory Clear
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// Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.
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//
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OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)
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Field (TNVS, AnyAcc, NoLock, Preserve)
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{
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PPIN, 8, // Software SMI for Physical Presence Interface
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PPIP, 32, // Used for save physical presence parameter
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PPRP, 32, // Physical Presence request operation response
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PPRQ, 32, // Physical Presence request operation
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PPRM, 32, // Physical Presence request operation parameter
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LPPR, 32, // Last Physical Presence request operation
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FRET, 32, // Physical Presence function return code
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MCIN, 8, // Software SMI for Memory Clear Interface
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MCIP, 32, // Used for save the Mor parameter
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MORD, 32, // Memory Overwrite Request Data
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MRET, 32, // Memory Overwrite function return code
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UCRQ, 32, // Physical Presence request operation to Get User Confirmation Status
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IRQN, 32, // IRQ Number for _CRS
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SFRB, 8 // Is shortformed Pkglength for resource buffer
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}
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//
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// Possible resource settings returned by _PRS method
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// RESS : ResourceTemplate with PkgLength <=63
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// RESL : ResourceTemplate with PkgLength > 63
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//
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// The format of the data has to follow the same format as
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// _CRS (according to ACPI spec).
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//
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Name (RESS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10}
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})
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Name (RESL, ResourceTemplate() {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
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})
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//
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// Current resource settings for _CRS method
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//
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Name(RES0, ResourceTemplate () {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG0)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}
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})
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Name(RES1, ResourceTemplate () {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG1)
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})
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//
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// Return the resource consumed by TPM device.
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//
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Method(_CRS,0,Serialized)
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{
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//
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// IRQNum = 0 means disable IRQ support
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//
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If (LEqual(IRQN, 0)) {
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Return (RES1)
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}
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Else
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{
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CreateDWordField(RES0, ^INTR._INT, LIRQ)
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Store(IRQN, LIRQ)
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Return (RES0)
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}
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}
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//
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// Set resources consumed by the TPM device. This is used to
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// assign an interrupt number to the device. The input byte stream
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// has to be the same as returned by _CRS (according to ACPI spec).
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//
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// Platform may choose to override this function with specific interrupt
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// programing logic to replace FIFO/TIS SIRQ registers programing
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//
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Method(_SRS,1,Serialized)
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{
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//
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// Do not configure Interrupt if IRQ Num is configured 0 by default
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//
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If (LNotEqual(IRQN, 0)) {
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//
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// Update resource descriptor
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// Use the field name to identify the offsets in the argument
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// buffer and RES0 buffer.
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//
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CreateDWordField(Arg0, ^INTR._INT, IRQ0)
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CreateDWordField(RES0, ^INTR._INT, LIRQ)
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Store(IRQ0, LIRQ)
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Store(IRQ0, IRQN)
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CreateBitField(Arg0, ^INTR._HE, ITRG)
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CreateBitField(RES0, ^INTR._HE, LTRG)
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Store(ITRG, LTRG)
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CreateBitField(Arg0, ^INTR._LL, ILVL)
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CreateBitField(RES0, ^INTR._LL, LLVL)
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Store(ILVL, LLVL)
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//
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// Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest
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// nibble.
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// 0000 - FIFO interface as defined in PTP for TPM 2.0 is active
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// 1111 - FIFO interface as defined in TIS1.3 is active
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//
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If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {
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//
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// If FIFO interface, interrupt vector register is
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// available. TCG PTP specification allows only
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// values 1..15 in this field. For other interrupts
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// the field should stay 0.
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//
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If (LLess (IRQ0, 16)) {
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Store (And(IRQ0, 0xF), INTV)
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}
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//
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// Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4
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// contains settings for interrupt polarity.
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// The other bits of the byte enable individual interrupts.
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// They should be all be zero, but to avoid changing the
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// configuration, the other bits are be preserved.
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// 00 - high level
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// 01 - low level
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// 10 - rising edge
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// 11 - falling edge
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//
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// ACPI spec definitions:
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// _HE: '1' is Edge, '0' is Level
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// _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)
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//
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If (LEqual (ITRG, 1)) {
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Or(INTE, 0x00000010, INTE)
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} Else {
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And(INTE, 0xFFFFFFEF, INTE)
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}
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if (LEqual (ILVL, 0)) {
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Or(INTE, 0x00000008, INTE)
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} Else {
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And(INTE, 0xFFFFFFF7, INTE)
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}
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}
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}
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}
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Method(_PRS,0,Serialized)
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{
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//
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// IRQNum = 0 means disable IRQ support
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//
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If (LEqual(IRQN, 0)) {
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Return (RES1)
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} ElseIf(LEqual(SFRB, 0)) {
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//
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// Long format. Possible resources PkgLength > 63
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//
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Return (RESL)
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} Else {
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//
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// Short format. Possible resources PkgLength <=63
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//
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Return (RESS)
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}
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}
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Method (PTS, 1, Serialized)
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{
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//
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// Detect Sx state for MOR, only S4, S5 need to handle
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//
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If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))
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{
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//
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// Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.
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//
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If (LNot (And (MORD, 0x10)))
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{
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//
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// Trigger the SMI through ACPI _PTS method.
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//
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Store (0x02, MCIP)
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//
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// Trigger the SMI interrupt
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//
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Store (MCIN, IOB2)
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}
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}
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Return (0)
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}
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Method (_STA, 0)
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{
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if (LEqual (ACC0, 0xff))
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{
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Return (0)
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}
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Return (0x0f)
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}
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//
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// TCG Hardware Information
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//
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Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj
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{
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//
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// Switch by function index
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//
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Switch (ToInteger(Arg0))
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{
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Case (0)
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{
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//
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// Standard query
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//
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Return (Buffer () {0x03})
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}
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Case (1)
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{
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//
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// Return failure if no TPM present
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//
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Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})
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if (LEqual (_STA (), 0x00))
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{
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Return (Package () {0x00})
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}
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//
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// Return TPM version
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//
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Return (TPMV)
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}
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Default {BreakPoint}
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}
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Return (Buffer () {0})
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}
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Name(TPM2, Package (0x02){
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Zero,
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Zero
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})
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Name(TPM3, Package (0x03){
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Zero,
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Zero,
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Zero
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})
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//
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// TCG Physical Presence Interface
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//
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Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj
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{
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//
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// Switch by function index
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//
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Switch (ToInteger(Arg0))
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{
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Case (0)
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{
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//
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// Standard query, supports function 1-8
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//
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Return (Buffer () {0xFF, 0x01})
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}
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Case (1)
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{
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//
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// a) Get Physical Presence Interface Version
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//
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Return ("$PV")
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}
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Case (2)
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{
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//
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// b) Submit TPM Operation Request to Pre-OS Environment
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//
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Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
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Store (0, PPRM)
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Store (0x02, PPIP)
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//
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// Trigger the SMI interrupt
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//
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Store (PPIN, IOB2)
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Return (FRET)
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}
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Case (3)
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{
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//
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// c) Get Pending TPM Operation Requested By the OS
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//
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Store (PPRQ, Index (TPM2, 0x01))
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Return (TPM2)
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}
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Case (4)
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{
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//
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// d) Get Platform-Specific Action to Transition to Pre-OS Environment
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//
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Return (2)
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}
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Case (5)
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{
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//
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// e) Return TPM Operation Response to OS Environment
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//
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Store (0x05, PPIP)
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//
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// Trigger the SMI interrupt
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//
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Store (PPIN, IOB2)
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Store (LPPR, Index (TPM3, 0x01))
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Store (PPRP, Index (TPM3, 0x02))
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Return (TPM3)
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}
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Case (6)
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{
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//
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// f) Submit preferred user language (Not implemented)
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//
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Return (3)
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}
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Case (7)
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{
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//
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// g) Submit TPM Operation Request to Pre-OS Environment 2
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//
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Store (7, PPIP)
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Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
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Store (0, PPRM)
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If (LEqual (PPRQ, 23)) {
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Store (DerefOf (Index (Arg1, 0x01)), PPRM)
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}
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//
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// Trigger the SMI interrupt
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//
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Store (PPIN, IOB2)
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Return (FRET)
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}
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Case (8)
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{
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//
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// e) Get User Confirmation Status for Operation
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//
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Store (8, PPIP)
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Store (DerefOf (Index (Arg1, 0x00)), UCRQ)
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//
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// Trigger the SMI interrupt
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//
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Store (PPIN, IOB2)
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Return (FRET)
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}
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Default {BreakPoint}
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}
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Return (1)
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}
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Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj
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{
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//
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// Switch by function index
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//
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Switch (ToInteger (Arg0))
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{
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Case (0)
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{
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//
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// Standard query, supports function 1-1
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//
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Return (Buffer () {0x03})
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}
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Case (1)
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{
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//
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// Save the Operation Value of the Request to MORD (reserved memory)
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//
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Store (DerefOf (Index (Arg1, 0x00)), MORD)
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//
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// Trigger the SMI through ACPI _DSM method.
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//
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Store (0x01, MCIP)
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//
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// Trigger the SMI interrupt
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//
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Store (MCIN, IOB2)
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Return (MRET)
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}
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Default {BreakPoint}
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}
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Return (1)
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}
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Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})
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{
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//
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// TCG Hardware Information
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//
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If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
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{
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Return (HINF (Arg2))
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}
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//
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// TCG Physical Presence Interface
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//
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If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))
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{
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Return (TPPI (Arg2, Arg3))
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}
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//
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// TCG Memory Clear Interface
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//
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If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
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{
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Return (TMCI (Arg2, Arg3))
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}
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Return (Buffer () {0})
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}
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}
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}
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}
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