mirror of https://github.com/acidanthera/audk.git
151 lines
6.4 KiB
C
151 lines
6.4 KiB
C
/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_VEXPRESS_H__
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#define __ARM_VEXPRESS_H__
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/*******************************************
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// Platform Memory Map
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*******************************************/
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// Can be NOR0, NOR1, DRAM
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#define ARM_VE_REMAP_BASE 0x00000000
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#define ARM_VE_REMAP_SZ 0x04000000
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000 /* 256 MB */
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#define ARM_VE_BOARD_PERIPH_BASE 0x10000000
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#define ARM_VE_CHIP_PERIPH_BASE 0x10020000
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// SMC
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#define ARM_VE_SMC_BASE 0x40000000
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#define ARM_VE_SMC_SZ 0x1C000000
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// NOR Flash 1
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#define ARM_VE_SMB_NOR0_BASE 0x40000000
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#define ARM_VE_SMB_NOR0_SZ 0x04000000 /* 64 MB */
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// NOR Flash 2
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#define ARM_VE_SMB_NOR1_BASE 0x44000000
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#define ARM_VE_SMB_NOR1_SZ 0x04000000 /* 64 MB */
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x48000000
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#define ARM_VE_SMB_SRAM_SZ 0x02000000 /* 32 MB */
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// USB, Ethernet, VRAM
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#define ARM_VE_SMB_PERIPH_BASE 0x4C000000
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#define ARM_VE_SMB_PERIPH_VRAM 0x4C000000
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#define ARM_VE_SMB_PERIPH_SZ 0x04000000 /* 32 MB */
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// DRAM
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#define ARM_VE_DRAM_BASE 0x60000000
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#define ARM_VE_DRAM_SZ 0x40000000
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// External AXI between daughterboards (Logic Tile)
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#define ARM_VE_EXT_AXI_BASE 0xE0000000
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#define ARM_VE_EXT_AXI_SZ 0x20000000
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/*******************************************
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// Motherboard peripherals
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*******************************************/
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// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
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#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
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// SP810 Controller
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#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
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// Uart0
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#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)
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#define PL011_CONSOLE_UART_SPEED 38400
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// SP804 Timer Bases
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#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)
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// Dynamic Memory Controller Base
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#define ARM_VE_DMC_BASE 0x100E0000
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// Static Memory Controller Base
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#define ARM_VE_SMC_CTRL_BASE 0x100E1000
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// System Configuration Controller register Base addresses
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//#define ARM_VE_SYS_CFG_CTRL_BASE 0x100E2000
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#define ARM_VE_SYS_CFGRW0_REG 0x100E2000
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#define ARM_VE_SYS_CFGRW1_REG 0x100E2004
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#define ARM_VE_SYS_CFGRW2_REG 0x100E2008
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#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000
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#define ARM_VE_CFGRW1_REMAP_NOR0 0
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#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)
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#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)
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#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)
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// TZPC Base Address
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#define ARM_VE_TZPC_BASE 0x100E6000
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// PL301 Fast AXI Base Address
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#define ARM_VE_FAXI_BASE 0x100E9000
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// TZASC Defintions
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#define ARM_VE_TZASC_BASE 0x100EC000
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#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)
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#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)
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#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)
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#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)
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#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
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#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
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// L2x0 Cache Controller Base Address
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//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
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/*******************************************
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// Interrupt Map
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*******************************************/
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// Timer Interrupts
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#define TIMER01_INTERRUPT_NUM 34
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#define TIMER23_INTERRUPT_NUM 35
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/*******************************************
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// EFI Memory Map in Permanent Memory (DRAM)
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*******************************************/
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// This region is allocated at the bottom of the DRAM. It will be used
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// for fixed address allocations such as Vector Table
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#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
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// This region is the memory declared to PEI as permanent memory for PEI
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// and DXE. EFI stacks and heaps will be declared in this region.
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#define ARM_VE_EFI_MEMORY_REGION_SZ 0x1000000
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#endif
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