mirror of https://github.com/acidanthera/audk.git
4904a2b1ec
In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> |
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| .. | ||
| BaseRiscV64CpuExceptionHandlerLib | ||
| BaseRiscV64CpuTimerLib | ||
| BaseUefiCpuLib | ||
| BaseXApicLib | ||
| BaseXApicX2ApicLib | ||
| CcExitLibNull | ||
| CpuCacheInfoLib | ||
| CpuCommonFeaturesLib | ||
| CpuExceptionHandlerLib | ||
| CpuPageTableLib | ||
| CpuTimerLib | ||
| MicrocodeLib | ||
| MpInitLib | ||
| MpInitLibUp | ||
| MtrrLib | ||
| PlatformSecLibNull | ||
| RegisterCpuFeaturesLib | ||
| SecPeiDxeTimerLibUefiCpu | ||
| SmmCpuFeaturesLib | ||
| SmmCpuPlatformHookLibNull | ||
| SmmCpuRendezvousLib | ||