mirror of https://github.com/acidanthera/audk.git
451 lines
14 KiB
C
451 lines
14 KiB
C
/** @file
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Private Header file for Usb Host Controller PEIM
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_PEI_XHCI_REG_H_
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#define _EFI_PEI_XHCI_REG_H_
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//
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// Capability registers offset
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//
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#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
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#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
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#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
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#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
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#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
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#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
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#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
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#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
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//
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// Operational registers offset
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//
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#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
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#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
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#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
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#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
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#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
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#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
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#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
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#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
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//
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// Runtime registers offset
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//
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#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
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#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
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#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
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#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
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#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
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#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
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//
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// Register Bit Definition
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//
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#define XHC_USBCMD_RUN BIT0 // Run/Stop
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#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
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#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
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#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
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#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
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#define XHC_USBSTS_HSE BIT2 // Host System Error
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#define XHC_USBSTS_EINT BIT3 // Event Interrupt
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#define XHC_USBSTS_PCD BIT4 // Port Change Detect
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#define XHC_USBSTS_SSS BIT8 // Save State Status
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#define XHC_USBSTS_RSS BIT9 // Restore State Status
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#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
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#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
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#define XHC_USBSTS_HCE BIT12 // Host Controller Error
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#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
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#define XHC_CRCR_RCS BIT0 // Ring Cycle State
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#define XHC_CRCR_CS BIT1 // Command Stop
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#define XHC_CRCR_CA BIT2 // Command Abort
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#define XHC_CRCR_CRR BIT3 // Command Ring Running
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#define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
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#define XHC_PORTSC_CCS BIT0 // Current Connect Status
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#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
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#define XHC_PORTSC_OCA BIT3 // Over-current Active
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#define XHC_PORTSC_RESET BIT4 // Port Reset
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#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
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#define XHC_PORTSC_PP BIT9 // Port Power
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#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
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#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
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#define XHC_PORTSC_CSC BIT17 // Connect Status Change
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#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
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#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
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#define XHC_PORTSC_OCC BIT20 // Over-Current Change
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#define XHC_PORTSC_PRC BIT21 // Port Reset Change
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#define XHC_PORTSC_PLC BIT22 // Port Link State Change
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#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
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#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
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#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
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#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
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#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
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#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
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#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
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#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
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#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
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#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
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#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
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#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
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#define XHC_IMAN_IP BIT0 // Interrupt Pending
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#define XHC_IMAN_IE BIT1 // Interrupt Enable
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#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
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#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
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#pragma pack (1)
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typedef struct {
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UINT8 MaxSlots; // Number of Device Slots
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UINT16 MaxIntrs:11; // Number of Interrupters
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UINT16 Rsvd:5;
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UINT8 MaxPorts; // Number of Ports
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} HCSPARAMS1;
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//
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// Structural Parameters 1 Register Bitmap Definition
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//
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typedef union {
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UINT32 Dword;
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HCSPARAMS1 Data;
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} XHC_HCSPARAMS1;
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typedef struct {
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UINT32 Ist:4; // Isochronous Scheduling Threshold
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UINT32 Erst:4; // Event Ring Segment Table Max
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UINT32 Rsvd:13;
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UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
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UINT32 Spr:1; // Scratchpad Restore
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UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
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} HCSPARAMS2;
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//
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// Structural Parameters 2 Register Bitmap Definition
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//
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typedef union {
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UINT32 Dword;
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HCSPARAMS2 Data;
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} XHC_HCSPARAMS2;
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typedef struct {
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UINT16 Ac64:1; // 64-bit Addressing Capability
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UINT16 Bnc:1; // BW Negotiation Capability
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UINT16 Csz:1; // Context Size
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UINT16 Ppc:1; // Port Power Control
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UINT16 Pind:1; // Port Indicators
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UINT16 Lhrc:1; // Light HC Reset Capability
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UINT16 Ltc:1; // Latency Tolerance Messaging Capability
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UINT16 Nss:1; // No Secondary SID Support
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UINT16 Pae:1; // Parse All Event Data
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UINT16 Rsvd:3;
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UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
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UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
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} HCCPARAMS;
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//
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// Capability Parameters Register Bitmap Definition
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//
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typedef union {
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UINT32 Dword;
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HCCPARAMS Data;
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} XHC_HCCPARAMS;
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#pragma pack ()
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//
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// XHCi Data and Ctrl Structures
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//
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#pragma pack(1)
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typedef struct {
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UINT8 Pi;
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UINT8 SubClassCode;
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UINT8 BaseCode;
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} USB_CLASSC;
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typedef struct {
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UINT8 Length;
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UINT8 DescType;
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UINT8 NumPorts;
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UINT16 HubCharacter;
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UINT8 PwrOn2PwrGood;
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UINT8 HubContrCurrent;
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UINT8 Filler[16];
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} EFI_USB_HUB_DESCRIPTOR;
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#pragma pack()
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//
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// Hub Class Feature Selector for Clear Port Feature Request
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// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
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// For more details, Please refer to USB 3.0 Spec Table 10-7.
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//
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typedef enum {
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Usb3PortBHPortReset = 28,
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Usb3PortBHPortResetChange = 29
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} XHC_PORT_FEATURE;
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//
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// Structure to map the hardware port states to the
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// UEFI's port states.
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//
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typedef struct {
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UINT32 HwState;
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UINT16 UefiState;
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} USB_PORT_STATE_MAP;
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//
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// Structure to map the hardware port states to feature selector for clear port feature request.
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//
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typedef struct {
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UINT32 HwState;
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UINT16 Selector;
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} USB_CLEAR_PORT_MAP;
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/**
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Read XHCI Operation register.
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@param Xhc The XHCI device.
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@param Offset The operation register offset.
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@retval the register content read.
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**/
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UINT32
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XhcPeiReadOpReg (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset
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);
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/**
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Write the data to the XHCI operation register.
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@param Xhc The XHCI device.
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@param Offset The operation register offset.
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@param Data The data to write.
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**/
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VOID
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XhcPeiWriteOpReg (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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);
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/**
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Set one bit of the operational register while keeping other bits.
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@param Xhc The XHCI device.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcPeiSetOpRegBit (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Clear one bit of the operational register while keeping other bits.
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@param Xhc The XHCI device.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to clear.
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**/
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VOID
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XhcPeiClearOpRegBit (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Wait the operation register's bit as specified by Bit
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to be set (or clear).
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@param Xhc The XHCI device.
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@param Offset The offset of the operational register.
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@param Bit The bit of the register to wait for.
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@param WaitToSet Wait the bit to set or clear.
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@param Timeout The time to wait before abort (in millisecond, ms).
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@retval EFI_SUCCESS The bit successfully changed by host controller.
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@retval EFI_TIMEOUT The time out occurred.
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**/
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EFI_STATUS
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XhcPeiWaitOpRegBit (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit,
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IN BOOLEAN WaitToSet,
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IN UINT32 Timeout
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);
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/**
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Write the data to the XHCI door bell register.
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@param Xhc The XHCI device.
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@param Offset The offset of the door bell register.
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@param Data The data to write.
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**/
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VOID
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XhcPeiWriteDoorBellReg (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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);
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/**
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Read XHCI runtime register.
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@param Xhc The XHCI device.
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@param Offset The offset of the runtime register.
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@return The register content read
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**/
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UINT32
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XhcPeiReadRuntimeReg (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset
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);
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/**
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Write the data to the XHCI runtime register.
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@param Xhc The XHCI device.
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@param Offset The offset of the runtime register.
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@param Data The data to write.
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**/
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VOID
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XhcPeiWriteRuntimeReg (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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);
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/**
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Set one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI device.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcPeiSetRuntimeRegBit (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Clear one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI device.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcPeiClearRuntimeRegBit (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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);
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/**
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Check whether Xhc is halted.
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@param Xhc The XHCI device.
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@retval TRUE The controller is halted.
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@retval FALSE The controller isn't halted.
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**/
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BOOLEAN
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XhcPeiIsHalt (
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IN PEI_XHC_DEV *Xhc
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);
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/**
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Check whether system error occurred.
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@param Xhc The XHCI device.
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@retval TRUE System error happened.
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@retval FALSE No system error.
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**/
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BOOLEAN
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XhcPeiIsSysError (
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IN PEI_XHC_DEV *Xhc
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);
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/**
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Reset the host controller.
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@param Xhc The XHCI device.
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@param Timeout Time to wait before abort (in millisecond, ms).
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@retval EFI_TIMEOUT The transfer failed due to time out.
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@retval Others Failed to reset the host.
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**/
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EFI_STATUS
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XhcPeiResetHC (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Timeout
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);
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/**
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Halt the host controller.
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@param Xhc The XHCI device.
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@param Timeout Time to wait before abort.
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@retval EFI_TIMEOUT Failed to halt the controller before Timeout.
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@retval EFI_SUCCESS The XHCI is halt.
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**/
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EFI_STATUS
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XhcPeiHaltHC (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Timeout
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);
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/**
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Set the XHCI to run.
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@param Xhc The XHCI device.
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@param Timeout Time to wait before abort.
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@retval EFI_SUCCESS The XHCI is running.
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@retval Others Failed to set the XHCI to run.
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**/
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EFI_STATUS
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XhcPeiRunHC (
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IN PEI_XHC_DEV *Xhc,
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IN UINT32 Timeout
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);
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#endif
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