mirror of https://github.com/acidanthera/audk.git
4aa7e66c06
Below code will calculate the reserved bus number for the each PF. Based on the VF routing ID algorithm, PFRid and LastVF in below code already sure that "All VFs and PFs must have distinct Routing IDs". PF will be assigned Routing ID based on secBusNumber, ReservedBusNum will add into SubBusNumber directly. So the SR-IOV device will be assigned bus range as SecBusNumber ~ (SubBusNumber=(SecBusNumber + ReservedBusNum)). Thus "+1" in below code will cause extra 1 bus, and introduce a bus hole. PFRid = EFI_PCI_RID (Bus, Device, Func); LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride; PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1); In SR-IOV spec, there is a note in section 2.1.2: Note: Bus Numbers are a constrained resource. Devices are strongly encouraged to avoid leaving ?holes? in their Bus Number usage to avoid wasting Bus Numbers So the issue can be fixed with below code change. PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus); https://bugzilla.tianocore.org/show_bug.cgi?id=4069 Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> |
||
|---|---|---|
| .. | ||
| EhciDxe | ||
| EhciPei | ||
| IdeBusPei | ||
| IncompatiblePciDeviceSupportDxe | ||
| NonDiscoverablePciDeviceDxe | ||
| NvmExpressDxe | ||
| NvmExpressPei | ||
| PciBusDxe | ||
| PciHostBridgeDxe | ||
| PciSioSerialDxe | ||
| SataControllerDxe | ||
| SdMmcPciHcDxe | ||
| SdMmcPciHcPei | ||
| UfsPciHcDxe | ||
| UfsPciHcPei | ||
| UhciDxe | ||
| UhciPei | ||
| XhciDxe | ||
| XhciPei | ||