mirror of https://github.com/acidanthera/audk.git
179 lines
5.1 KiB
NASM
179 lines
5.1 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiException.asm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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EXTERNDEF gcStmPsd:BYTE
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EXTERNDEF SmmStmExceptionHandler:PROC
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EXTERNDEF SmmStmSetup:PROC
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EXTERNDEF SmmStmTeardown:PROC
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EXTERNDEF gStmXdSupported:BYTE
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CODE_SEL EQU 38h
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DATA_SEL EQU 20h
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TR_SEL EQU 40h
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MSR_IA32_MISC_ENABLE EQU 1A0h
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MSR_EFER EQU 0c0000080h
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MSR_EFER_XD EQU 0800h
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.data
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;
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; This structure serves as a template for all processors.
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;
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gcStmPsd LABEL BYTE
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DB 'TXTPSSIG'
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DW PSD_SIZE
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DW 1 ; Version
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DD 0 ; LocalApicId
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DB 0Fh ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
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DB 0 ; BIOS to STM
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DB 0 ; STM to BIOS
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DB 0
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW TR_SEL
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DW 0
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DQ 0 ; SmmCr3
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DQ _OnStmSetup
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DQ _OnStmTeardown
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DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
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DQ 0 ; SmmSmiHandlerRsp
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DQ 0
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DD 0
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DD 80010100h ; RequiredStmSmmRevId
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DQ _OnException
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DQ 0 ; ExceptionStack
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DW DATA_SEL
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DW 01Fh ; ExceptionFilter
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DD 0
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DQ 0
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DQ 0 ; BiosHwResourceRequirementsPtr
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DQ 0 ; AcpiRsdp
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DB 0 ; PhysicalAddressBits
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PSD_SIZE = $ - offset gcStmPsd
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.code
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;------------------------------------------------------------------------------
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; SMM Exception handlers
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;------------------------------------------------------------------------------
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_OnException PROC
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mov rcx, rsp
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add rsp, -28h
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call SmmStmExceptionHandler
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add rsp, 28h
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mov ebx, eax
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mov eax, 4
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DB 0fh, 01h, 0c1h ; VMCALL
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jmp $
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_OnException ENDP
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_OnStmSetup PROC
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;
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; Check XD disable bit
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;
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xor r8, r8
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @StmXdDone1
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz @f
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and dx, 0FFFBh ; clear XD Disable bit if it is set
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wrmsr
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@@:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone1:
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push r8
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add rsp, -20h
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call SmmStmSetup
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add rsp, 20h
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @f
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pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz @f
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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@@:
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rsm
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_OnStmSetup ENDP
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_OnStmTeardown PROC
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;
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; Check XD disable bit
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;
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xor r8, r8
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @StmXdDone2
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz @f
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and dx, 0FFFBh ; clear XD Disable bit if it is set
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wrmsr
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@@:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone2:
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push r8
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add rsp, -20h
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call SmmStmTeardown
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add rsp, 20h
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mov rax, offset ASM_PFX(gStmXdSupported)
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mov al, [rax]
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cmp al, 0
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jz @f
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pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz @f
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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@@:
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rsm
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_OnStmTeardown ENDP
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END
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