mirror of https://github.com/acidanthera/audk.git
190 lines
6.9 KiB
C
190 lines
6.9 KiB
C
/** @file
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Ia32-specific functionality for DxeLoad.
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Copyright (c) 2006 - 2008, Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeIpl.h"
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#include "VirtualMemory.h"
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//
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// Global Descriptor Table (GDT)
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//
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GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {
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/* selector { Global Segment Descriptor } */
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/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor
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/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor
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/* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor
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/* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
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/* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system code segment descriptor
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/* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
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/* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
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/* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}}, //system code segment descriptor
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/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
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};
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//
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// IA32 Gdt register
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//
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GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt = {
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sizeof (gGdtEntries) - 1,
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(UINTN) gGdtEntries
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};
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GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor = {
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sizeof (X64_IDT_GATE_DESCRIPTOR) * 32 - 1,
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0
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};
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/**
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Transfers control to DxeCore.
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This function performs a CPU architecture specific operations to execute
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the entry point of DxeCore with the parameters of HobList.
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It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
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@param DxeCoreEntryPoint The entry point of DxeCore.
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@param HobList The start of HobList passed to DxeCore.
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**/
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VOID
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HandOffToDxeCore (
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IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
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IN EFI_PEI_HOB_POINTERS HobList
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)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS BaseOfStack;
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EFI_PHYSICAL_ADDRESS TopOfStack;
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UINTN PageTables;
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X64_IDT_GATE_DESCRIPTOR *IdtTable;
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UINTN SizeOfTemplate;
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VOID *TemplateBase;
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EFI_PHYSICAL_ADDRESS VectorAddress;
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UINT32 Index;
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Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);
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ASSERT_EFI_ERROR (Status);
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if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {
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//
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// Compute the top of the stack we were allocated, which is used to load X64 dxe core.
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// Pre-allocate a 32 bytes which confroms to x64 calling convention.
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//
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// The first four parameters to a function are passed in rcx, rdx, r8 and r9.
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// Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the
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// register parameters is reserved on the stack, in case the called function
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// wants to spill them; this is important if the function is variadic.
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//
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TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;
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//
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// x64 Calling Conventions requires that the stack must be aligned to 16 bytes
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//
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TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);
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//
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// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA
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// memory, it may be corrupted when copying FV to high-end memory
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//
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AsmWriteGdtr (&gGdt);
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables ();
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//
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// End of PEI phase signal
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//
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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ASSERT_EFI_ERROR (Status);
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AsmWriteCr3 (PageTables);
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob (BaseOfStack, STACK_SIZE);
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SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);
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Status = PeiServicesAllocatePages (
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EfiBootServicesData,
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EFI_SIZE_TO_PAGES((SizeOfTemplate + sizeof (X64_IDT_GATE_DESCRIPTOR)) * 32),
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&VectorAddress
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);
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ASSERT_EFI_ERROR (Status);
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IdtTable = (X64_IDT_GATE_DESCRIPTOR *) (UINTN) (VectorAddress + SizeOfTemplate * 32);
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for (Index = 0; Index < 32; Index++) {
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IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;
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IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;
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IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;
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IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;
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IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));
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IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));
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IdtTable[Index].Reserved = 0;
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CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);
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AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);
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VectorAddress += SizeOfTemplate;
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}
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gLidtDescriptor.Base = (UINTN) IdtTable;
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AsmWriteIdtr (&gLidtDescriptor);
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//
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// Go to Long Mode and transfer control to DxeCore.
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// Interrupts will not get turned on until the CPU AP is loaded.
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// Call x64 drivers passing in single argument, a pointer to the HOBs.
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//
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AsmEnablePaging64 (
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SYS_CODE64_SEL,
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DxeCoreEntryPoint,
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(EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),
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0,
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TopOfStack
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);
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} else {
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//
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// Compute the top of the stack we were allocated. Pre-allocate a UINTN
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// for safety.
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//
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TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;
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TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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//
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// End of PEI phase signal
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//
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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ASSERT_EFI_ERROR (Status);
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob (BaseOfStack, STACK_SIZE);
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//
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// Transfer the control to the entry point of DxeCore.
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//
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
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HobList.Raw,
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NULL,
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(VOID *) (UINTN) TopOfStack
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);
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}
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}
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