mirror of https://github.com/acidanthera/audk.git
689 lines
17 KiB
C
689 lines
17 KiB
C
/** @file
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This file implement the MMC Host Protocol for the DesignWare eMMC.
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Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Protocol/MmcHost.h>
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#include "DwEmmc.h"
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#define DWEMMC_DESC_PAGE 1
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#define DWEMMC_BLOCK_SIZE 512
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#define DWEMMC_DMA_BUF_SIZE (512 * 8)
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#define DWEMMC_MAX_DESC_PAGES 512
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typedef struct {
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UINT32 Des0;
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UINT32 Des1;
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UINT32 Des2;
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UINT32 Des3;
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} DWEMMC_IDMAC_DESCRIPTOR;
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EFI_MMC_HOST_PROTOCOL *gpMmcHost;
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DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc;
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EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
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STATIC UINT32 mDwEmmcCommand;
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STATIC UINT32 mDwEmmcArgument;
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EFI_STATUS
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DwEmmcReadBlockData (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Length,
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IN UINT32* Buffer
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);
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BOOLEAN
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DwEmmcIsPowerOn (
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VOID
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)
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{
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return TRUE;
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}
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EFI_STATUS
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DwEmmcInitialize (
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VOID
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)
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{
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DEBUG ((DEBUG_BLKIO, "DwEmmcInitialize()"));
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return EFI_SUCCESS;
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}
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BOOLEAN
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DwEmmcIsCardPresent (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return TRUE;
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}
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BOOLEAN
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DwEmmcIsReadOnly (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return FALSE;
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}
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BOOLEAN
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DwEmmcIsDmaSupported (
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IN EFI_MMC_HOST_PROTOCOL *This
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)
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{
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return TRUE;
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}
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EFI_STATUS
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DwEmmcBuildDevicePath (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
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)
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{
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EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
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NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
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CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
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*DevicePath = NewDevicePathNode;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcUpdateClock (
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VOID
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)
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{
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UINT32 Data;
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/* CMD_UPDATE_CLK */
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Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
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BIT_CMD_START;
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MmioWrite32 (DWEMMC_CMD, Data);
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while (1) {
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Data = MmioRead32 (DWEMMC_CMD);
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if (!(Data & CMD_START_BIT)) {
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break;
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}
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Data = MmioRead32 (DWEMMC_RINTSTS);
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if (Data & DWEMMC_INT_HLE) {
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Print (L"failed to update mmc clock frequency\n");
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return EFI_DEVICE_ERROR;
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}
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcSetClock (
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IN UINTN ClockFreq
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)
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{
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UINT32 Divider, Rate, Data;
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EFI_STATUS Status;
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BOOLEAN Found = FALSE;
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for (Divider = 1; Divider < 256; Divider++) {
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Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
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if ((Rate / (2 * Divider)) <= ClockFreq) {
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Found = TRUE;
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break;
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}
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}
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if (Found == FALSE) {
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return EFI_NOT_FOUND;
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}
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// Wait until MMC is idle
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do {
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Data = MmioRead32 (DWEMMC_STATUS);
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} while (Data & DWEMMC_STS_DATA_BUSY);
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// Disable MMC clock first
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MmioWrite32 (DWEMMC_CLKENA, 0);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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MmioWrite32 (DWEMMC_CLKDIV, Divider);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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// Enable MMC clock
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MmioWrite32 (DWEMMC_CLKENA, 1);
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MmioWrite32 (DWEMMC_CLKSRC, 0);
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Status = DwEmmcUpdateClock ();
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ASSERT (!EFI_ERROR (Status));
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcNotifyState (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN MMC_STATE State
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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switch (State) {
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case MmcInvalidState:
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return EFI_INVALID_PARAMETER;
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case MmcHwInitializationState:
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MmioWrite32 (DWEMMC_PWREN, 1);
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// If device already turn on then restart it
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Data = DWEMMC_CTRL_RESET_ALL;
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MmioWrite32 (DWEMMC_CTRL, Data);
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do {
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// Wait until reset operation finished
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Data = MmioRead32 (DWEMMC_CTRL);
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} while (Data & DWEMMC_CTRL_RESET_ALL);
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// Setup clock that could not be higher than 400KHz.
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Status = DwEmmcSetClock (400000);
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ASSERT (!EFI_ERROR (Status));
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// Wait clock stable
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MicroSecondDelay (100);
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MmioWrite32 (DWEMMC_RINTSTS, ~0);
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MmioWrite32 (DWEMMC_INTMASK, 0);
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MmioWrite32 (DWEMMC_TMOUT, ~0);
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MmioWrite32 (DWEMMC_IDINTEN, 0);
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MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
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MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
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do {
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Data = MmioRead32 (DWEMMC_BMOD);
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} while (Data & DWEMMC_IDMAC_SWRESET);
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break;
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case MmcIdleState:
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break;
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case MmcReadyState:
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break;
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case MmcIdentificationState:
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break;
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case MmcStandByState:
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break;
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case MmcTransferState:
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break;
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case MmcSendingDataState:
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break;
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case MmcReceiveDataState:
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break;
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case MmcProgrammingState:
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break;
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case MmcDisconnectState:
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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// Need to prepare DMA buffer first before sending commands to MMC card
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BOOLEAN
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IsPendingReadCommand (
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IN MMC_CMD MmcCmd
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)
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{
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UINTN Mask;
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Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
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if ((MmcCmd & Mask) == Mask) {
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return TRUE;
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}
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return FALSE;
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}
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BOOLEAN
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IsPendingWriteCommand (
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IN MMC_CMD MmcCmd
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)
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{
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UINTN Mask;
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Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
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if ((MmcCmd & Mask) == Mask) {
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return TRUE;
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}
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return FALSE;
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}
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EFI_STATUS
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SendCommand (
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IN MMC_CMD MmcCmd,
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IN UINT32 Argument
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)
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{
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UINT32 Data, ErrMask;
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// Wait until MMC is idle
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do {
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Data = MmioRead32 (DWEMMC_STATUS);
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} while (Data & DWEMMC_STS_DATA_BUSY);
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MmioWrite32 (DWEMMC_RINTSTS, ~0);
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MmioWrite32 (DWEMMC_CMDARG, Argument);
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MmioWrite32 (DWEMMC_CMD, MmcCmd);
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ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
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DWEMMC_INT_RCRC | DWEMMC_INT_RE;
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ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
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do {
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MicroSecondDelay(500);
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Data = MmioRead32 (DWEMMC_RINTSTS);
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if (Data & ErrMask) {
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return EFI_DEVICE_ERROR;
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}
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if (Data & DWEMMC_INT_DTO) { // Transfer Done
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break;
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}
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} while (!(Data & DWEMMC_INT_CMD_DONE));
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return EFI_SUCCESS;
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}
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EFI_STATUS
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DwEmmcSendCommand (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN MMC_CMD MmcCmd,
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IN UINT32 Argument
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)
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{
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UINT32 Cmd = 0;
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EFI_STATUS Status = EFI_SUCCESS;
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switch (MMC_GET_INDX(MmcCmd)) {
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case MMC_INDX(0):
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Cmd = BIT_CMD_SEND_INIT;
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break;
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case MMC_INDX(1):
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Cmd = BIT_CMD_RESPONSE_EXPECT;
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break;
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case MMC_INDX(2):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
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BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
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break;
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case MMC_INDX(3):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_SEND_INIT;
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break;
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case MMC_INDX(7):
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if (Argument)
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
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else
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Cmd = 0;
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break;
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case MMC_INDX(8):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
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BIT_CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case MMC_INDX(9):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_LONG_RESPONSE;
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break;
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case MMC_INDX(12):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_STOP_ABORT_CMD;
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break;
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case MMC_INDX(13):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case MMC_INDX(16):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
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BIT_CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case MMC_INDX(17):
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case MMC_INDX(18):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
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BIT_CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case MMC_INDX(24):
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case MMC_INDX(25):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
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BIT_CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case MMC_INDX(30):
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
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BIT_CMD_DATA_EXPECTED;
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break;
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default:
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Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
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break;
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}
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Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
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if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
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mDwEmmcCommand = Cmd;
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mDwEmmcArgument = Argument;
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} else {
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Status = SendCommand (Cmd, Argument);
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}
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return Status;
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}
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EFI_STATUS
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DwEmmcReceiveResponse (
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IN EFI_MMC_HOST_PROTOCOL *This,
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IN MMC_RESPONSE_TYPE Type,
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IN UINT32* Buffer
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)
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{
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if (Buffer == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if ( (Type == MMC_RESPONSE_TYPE_R1)
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|| (Type == MMC_RESPONSE_TYPE_R1b)
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|| (Type == MMC_RESPONSE_TYPE_R3)
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|| (Type == MMC_RESPONSE_TYPE_R6)
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|| (Type == MMC_RESPONSE_TYPE_R7))
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{
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Buffer[0] = MmioRead32 (DWEMMC_RESP0);
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} else if (Type == MMC_RESPONSE_TYPE_R2) {
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Buffer[0] = MmioRead32 (DWEMMC_RESP0);
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Buffer[1] = MmioRead32 (DWEMMC_RESP1);
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Buffer[2] = MmioRead32 (DWEMMC_RESP2);
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Buffer[3] = MmioRead32 (DWEMMC_RESP3);
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}
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return EFI_SUCCESS;
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}
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VOID
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DwEmmcAdjustFifoThreshold (
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VOID
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)
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{
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/* DMA multiple transaction size map to reg value as array index */
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CONST UINT32 BurstSize[] = {1, 4, 8, 16, 32, 64, 128, 256};
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UINT32 BlkDepthInFifo, FifoThreshold, FifoWidth, FifoDepth;
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UINT32 BlkSize = DWEMMC_BLOCK_SIZE, Idx = 0, RxWatermark = 1, TxWatermark, TxWatermarkInvers;
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/* Skip FIFO adjustment if we do not have platform FIFO depth info */
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FifoDepth = PcdGet32 (PcdDwEmmcDxeFifoDepth);
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if (!FifoDepth) {
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return;
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}
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TxWatermark = FifoDepth / 2;
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TxWatermarkInvers = FifoDepth - TxWatermark;
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FifoWidth = DWEMMC_GET_HDATA_WIDTH (MmioRead32 (DWEMMC_HCON));
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if (!FifoWidth) {
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FifoWidth = 2;
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} else if (FifoWidth == 2) {
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FifoWidth = 8;
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} else {
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FifoWidth = 4;
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}
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BlkDepthInFifo = BlkSize / FifoWidth;
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Idx = ARRAY_SIZE (BurstSize) - 1;
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while (Idx && ((BlkDepthInFifo % BurstSize[Idx]) || (TxWatermarkInvers % BurstSize[Idx]))) {
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Idx--;
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}
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RxWatermark = BurstSize[Idx] - 1;
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FifoThreshold = DWEMMC_DMA_BURST_SIZE (Idx) | DWEMMC_FIFO_TWMARK (TxWatermark)
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| DWEMMC_FIFO_RWMARK (RxWatermark);
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MmioWrite32 (DWEMMC_FIFOTH, FifoThreshold);
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}
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EFI_STATUS
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PrepareDmaData (
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IN DWEMMC_IDMAC_DESCRIPTOR* IdmacDesc,
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IN UINTN Length,
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IN UINT32* Buffer
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)
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{
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UINTN Cnt, Blks, Idx, LastIdx;
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Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
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Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
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Length = DWEMMC_BLOCK_SIZE * Blks;
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for (Idx = 0; Idx < Cnt; Idx++) {
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(IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
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DWEMMC_IDMAC_DES0_DIC;
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(IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
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/* Buffer Address */
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(IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
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/* Next Descriptor Address */
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(IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
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(sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
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}
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/* First Descriptor */
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IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
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/* Last Descriptor */
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LastIdx = Cnt - 1;
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(IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
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(IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
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(IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
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(LastIdx * DWEMMC_DMA_BUF_SIZE));
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/* Set the Next field of Last Descriptor */
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(IdmacDesc + LastIdx)->Des3 = 0;
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MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
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return EFI_SUCCESS;
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}
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VOID
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StartDma (
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UINTN Length
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)
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{
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UINT32 Data;
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Data = MmioRead32 (DWEMMC_CTRL);
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Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
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MmioWrite32 (DWEMMC_CTRL, Data);
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Data = MmioRead32 (DWEMMC_BMOD);
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Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
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MmioWrite32 (DWEMMC_BMOD, Data);
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MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
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MmioWrite32 (DWEMMC_BYTCNT, Length);
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|
}
|
|
|
|
EFI_STATUS
|
|
DwEmmcReadBlockData (
|
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
|
IN EFI_LBA Lba,
|
|
IN UINTN Length,
|
|
IN UINT32* Buffer
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UINT32 DescPages, CountPerPage, Count;
|
|
EFI_TPL Tpl;
|
|
|
|
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
|
|
|
|
CountPerPage = EFI_PAGE_SIZE / 16;
|
|
Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
|
|
DescPages = (Count + CountPerPage - 1) / CountPerPage;
|
|
|
|
InvalidateDataCacheRange (Buffer, Length);
|
|
|
|
Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
|
|
if (EFI_ERROR (Status)) {
|
|
goto out;
|
|
}
|
|
|
|
WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
|
|
StartDma (Length);
|
|
|
|
Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
|
|
goto out;
|
|
}
|
|
out:
|
|
// Restore Tpl
|
|
gBS->RestoreTPL (Tpl);
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
DwEmmcWriteBlockData (
|
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
|
IN EFI_LBA Lba,
|
|
IN UINTN Length,
|
|
IN UINT32* Buffer
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UINT32 DescPages, CountPerPage, Count;
|
|
EFI_TPL Tpl;
|
|
|
|
Tpl = gBS->RaiseTPL (TPL_NOTIFY);
|
|
|
|
CountPerPage = EFI_PAGE_SIZE / 16;
|
|
Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
|
|
DescPages = (Count + CountPerPage - 1) / CountPerPage;
|
|
|
|
WriteBackDataCacheRange (Buffer, Length);
|
|
|
|
Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
|
|
if (EFI_ERROR (Status)) {
|
|
goto out;
|
|
}
|
|
|
|
WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
|
|
StartDma (Length);
|
|
|
|
Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
|
|
goto out;
|
|
}
|
|
out:
|
|
// Restore Tpl
|
|
gBS->RestoreTPL (Tpl);
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
DwEmmcSetIos (
|
|
IN EFI_MMC_HOST_PROTOCOL *This,
|
|
IN UINT32 BusClockFreq,
|
|
IN UINT32 BusWidth,
|
|
IN UINT32 TimingMode
|
|
)
|
|
{
|
|
EFI_STATUS Status = EFI_SUCCESS;
|
|
UINT32 Data;
|
|
|
|
if ((PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz) != 0) &&
|
|
(BusClockFreq > PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz))) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
if (TimingMode != EMMCBACKWARD) {
|
|
Data = MmioRead32 (DWEMMC_UHSREG);
|
|
switch (TimingMode) {
|
|
case EMMCHS52DDR1V2:
|
|
case EMMCHS52DDR1V8:
|
|
Data |= 1 << 16;
|
|
break;
|
|
case EMMCHS52:
|
|
case EMMCHS26:
|
|
Data &= ~(1 << 16);
|
|
break;
|
|
default:
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
MmioWrite32 (DWEMMC_UHSREG, Data);
|
|
}
|
|
|
|
switch (BusWidth) {
|
|
case 1:
|
|
MmioWrite32 (DWEMMC_CTYPE, 0);
|
|
break;
|
|
case 4:
|
|
MmioWrite32 (DWEMMC_CTYPE, 1);
|
|
break;
|
|
case 8:
|
|
MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
|
|
break;
|
|
default:
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
if (BusClockFreq) {
|
|
Status = DwEmmcSetClock (BusClockFreq);
|
|
}
|
|
return Status;
|
|
}
|
|
|
|
BOOLEAN
|
|
DwEmmcIsMultiBlock (
|
|
IN EFI_MMC_HOST_PROTOCOL *This
|
|
)
|
|
{
|
|
return TRUE;
|
|
}
|
|
|
|
EFI_MMC_HOST_PROTOCOL gMciHost = {
|
|
MMC_HOST_PROTOCOL_REVISION,
|
|
DwEmmcIsCardPresent,
|
|
DwEmmcIsReadOnly,
|
|
DwEmmcBuildDevicePath,
|
|
DwEmmcNotifyState,
|
|
DwEmmcSendCommand,
|
|
DwEmmcReceiveResponse,
|
|
DwEmmcReadBlockData,
|
|
DwEmmcWriteBlockData,
|
|
DwEmmcSetIos,
|
|
DwEmmcIsMultiBlock
|
|
};
|
|
|
|
EFI_STATUS
|
|
DwEmmcDxeInitialize (
|
|
IN EFI_HANDLE ImageHandle,
|
|
IN EFI_SYSTEM_TABLE *SystemTable
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
EFI_HANDLE Handle;
|
|
|
|
Handle = NULL;
|
|
|
|
DwEmmcAdjustFifoThreshold ();
|
|
gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
|
|
if (gpIdmacDesc == NULL) {
|
|
return EFI_BUFFER_TOO_SMALL;
|
|
}
|
|
|
|
DEBUG ((DEBUG_BLKIO, "DwEmmcDxeInitialize()\n"));
|
|
|
|
//Publish Component Name, BlockIO protocol interfaces
|
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
|
&Handle,
|
|
&gEfiMmcHostProtocolGuid, &gMciHost,
|
|
NULL
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|