Ray Ni 86ad762fa7 UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48 ... Today's behavior is to enable 5l paging when CPU supports it (CPUID[7,0].ECX.BIT[16] is set). The patch changes the behavior to enable 5l paging when two conditions are both met: 1. CPU supports it; 2. The max physical address bits is bigger than 48. Because 4-level paging can support to address physical address up to 2^48 - 1, there is no need to enable 5-level paging with max physical address bits <= 48. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>		2019-09-13 16:20:54 +08:00
..
Cet.nasm	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
MpFuncs.nasm	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
PageTbl.c	UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48	2019-09-13 16:20:54 +08:00
Semaphore.c	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
SmiEntry.nasm	UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48	2019-09-13 16:20:54 +08:00
SmiException.nasm	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
SmmFuncsArch.c	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
SmmInit.nasm	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00
SmmProfileArch.c	UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports	2019-07-12 15:13:51 +08:00
SmmProfileArch.h	UefiCpuPkg: Replace BSD License with BSD+Patent License	2019-04-09 10:58:28 -07:00