mirror of https://github.com/acidanthera/audk.git
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/** @file
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*
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* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef _ARM_GIC_V2_H_
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#define _ARM_GIC_V2_H_
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//
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// GIC definitions
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//
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//
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// GIC Distributor
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//
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#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
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#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
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#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
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// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
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#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
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#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
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#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
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#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
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#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
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#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
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// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
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#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
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// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
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#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
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#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
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#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
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// just one of these
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#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
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//
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// GIC Cpu interface
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//
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#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
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#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
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#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
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#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
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#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
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#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
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#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
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#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
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#define ARM_GIC_ICCIIDR 0xFC // Identification Register
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// Bit Mask for
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#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
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// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)
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#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
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VOID
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EFIAPI
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ArmGicV2SetupNonSecure (
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IN UINTN MpId,
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2EnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2DisableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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);
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UINTN
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EFIAPI
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ArmGicV2AcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2EndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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);
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#endif
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