mirror of https://github.com/acidanthera/audk.git
136 lines
4.4 KiB
C
136 lines
4.4 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Drivers/PL390Gic.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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*
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*/
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VOID
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EFIAPI
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PL390GicSetupNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
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// Check if there are any pending interrupts
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while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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// Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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}
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// Ensure all GIC interrupts are Non-Secure
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MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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// Ensure all interrupts can get through the priority mask
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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EFIAPI
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PL390GicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
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/*
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* Enable CPU interface in Secure world
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* Enable CPU inteface in Non-secure World
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* Signal Secure Interrupts to CPU using FIQ line *
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*/
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
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GIC_ICCICR_ENABLE_SECURE(1) |
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GIC_ICCICR_ENABLE_NS(1) |
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GIC_ICCICR_ACK_CTL(0) |
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GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
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GIC_ICCICR_USE_SBPR(0));
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}
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VOID
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EFIAPI
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PL390GicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
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}
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VOID
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EFIAPI
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PL390GicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList
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)
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{
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MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgiFrom (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgi2From (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId,
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IN INTN SgiId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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}
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