mirror of https://github.com/acidanthera/audk.git
101 lines
2.9 KiB
NASM
101 lines
2.9 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; First code executed by processor after resetting.
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; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
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;
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; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 16
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ALIGN 16
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;
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; Pad the image size to 4k when page tables are in VTF0
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;
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; If the VTF0 image has page tables built in, then we need to make
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; sure the end of VTF0 is 4k above where the page tables end.
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;
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; This is required so the page tables will be 4k aligned when VTF0 is
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; located just below 0x100000000 (4GB) in the firmware device.
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;
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%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
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TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
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%endif
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;
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; SEV-ES Processor Reset support
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;
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; sevEsResetBlock:
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; For the initial boot of an AP under SEV-ES, the "reset" RIP must be
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; programmed to the RAM area defined by SEV_ES_AP_RESET_IP. A known offset
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; and GUID will be used to locate this block in the firmware and extract
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; the build time RIP value. The GUID must always be 48 bytes from the
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; end of the firmware.
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;
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; 0xffffffca (-0x36) - IP value
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; 0xffffffcc (-0x34) - CS segment base [31:16]
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; 0xffffffce (-0x32) - Size of the SEV-ES reset block
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; 0xffffffd0 (-0x30) - SEV-ES reset block GUID
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; (00f771de-1a7e-4fcb-890e-68c77e2fb44e)
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;
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; A hypervisor reads the CS segement base and IP value. The CS segment base
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; value represents the high order 16-bits of the CS segment base, so the
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; hypervisor must left shift the value of the CS segement base by 16 bits to
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; form the full CS segment base for the CS segment register. It would then
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; program the EIP register with the IP value as read.
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;
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TIMES (32 - (sevEsResetBlockEnd - sevEsResetBlockStart)) DB 0
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sevEsResetBlockStart:
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DD SEV_ES_AP_RESET_IP
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DW sevEsResetBlockEnd - sevEsResetBlockStart
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DB 0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F
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DB 0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E
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sevEsResetBlockEnd:
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ALIGN 16
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applicationProcessorEntryPoint:
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;
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; Application Processors entry point
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;
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; GenFv generates code aligned on a 4k boundary which will jump to this
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; location. (0xffffffe0) This allows the Local APIC Startup IPI to be
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; used to wake up the application processors.
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;
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jmp EarlyApInitReal16
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ALIGN 8
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DD 0
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;
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; The VTF signature
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;
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; VTF-0 means that the VTF (Volume Top File) code does not require
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; any fixups.
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;
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vtfSignature:
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DB 'V', 'T', 'F', 0
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ALIGN 16
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resetVector:
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;
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; Reset Vector
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;
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; This is where the processor will begin execution
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;
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nop
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nop
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jmp EarlyBspInitReal16
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ALIGN 16
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fourGigabytes:
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