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audk/MdePkg/Library/BaseLib/RiscV64
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Abner Chang 7601b251fd MdePkg/BaseLib: BaseLib for RISCV64 architecture 
Add RISC-V RV64 BaseLib functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
 		2020-05-07 03:17:15 +00:00
..
CpuBreakpoint.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
CpuPause.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
DisableInterrupts.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
EnableInterrupts.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
FlushCache.S MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
GetInterruptState.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
InternalSwitchStack.c MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
RiscVCpuBreakpoint.S MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
RiscVCpuPause.S MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
RiscVInterrupt.S MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00
RiscVSetJumpLongJump.S MdePkg/BaseLib: BaseLib for RISCV64 architecture 2020-05-07 03:17:15 +00:00