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54d8d4dc97
Now that the AArch64 MMU code correctly identifies and handles naturally aligned regions of more than 2 MB in size, it will happily try to use block mappings at level 0 to map huge memory regions, such as the single cacheable 1:1 mapping we use for Xen domU to map the entire PA space. However, block mappings are not supported at level 0 so the resulting translation tables will be incorrect, causing execution to fail as soon as the MMU is enabled. So use level 1 as the minimum level at which to perform block translations. Reported-by: Julien Grall <julien.grall@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568 6f19259b-4bc3-4df7-8a09-765794883524