mirror of https://github.com/acidanthera/audk.git
1035 lines
29 KiB
C
1035 lines
29 KiB
C
/** @file
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The EHCI register operation routines.
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Copyright (c) 2007 - 2010, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Uhci.h"
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/**
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Create Frame List Structure.
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@param Uhc UHCI device.
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@retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
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@retval EFI_UNSUPPORTED Map memory fail.
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@retval EFI_SUCCESS Success.
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**/
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EFI_STATUS
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UhciInitFrameList (
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IN USB_HC_DEV *Uhc
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)
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{
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EFI_PHYSICAL_ADDRESS MappedAddr;
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EFI_STATUS Status;
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VOID *Buffer;
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VOID *Mapping;
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UINTN Pages;
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UINTN Bytes;
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UINTN Index;
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EFI_PHYSICAL_ADDRESS PhyAddr;
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//
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// The Frame List is a common buffer that will be
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// accessed by both the cpu and the usb bus master
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// at the same time. The Frame List ocupies 4K bytes,
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// and must be aligned on 4-Kbyte boundaries.
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//
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Bytes = 4096;
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Pages = EFI_SIZE_TO_PAGES (Bytes);
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Status = Uhc->PciIo->AllocateBuffer (
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Uhc->PciIo,
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AllocateAnyPages,
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EfiBootServicesData,
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Pages,
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&Buffer,
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0
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);
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if (EFI_ERROR (Status)) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = Uhc->PciIo->Map (
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Uhc->PciIo,
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EfiPciIoOperationBusMasterCommonBuffer,
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Buffer,
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&Bytes,
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&MappedAddr,
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&Mapping
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);
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if (EFI_ERROR (Status) || (Bytes != 4096)) {
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Status = EFI_UNSUPPORTED;
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goto ON_ERROR;
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}
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Uhc->FrameBase = (UINT32 *) (UINTN) Buffer;
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Uhc->FrameMapping = Mapping;
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//
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// Tell the Host Controller where the Frame List lies,
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// by set the Frame List Base Address Register.
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//
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UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (UINTN) MappedAddr);
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//
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// Allocate the QH used by sync interrupt/control/bulk transfer.
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// FS ctrl/bulk queue head is set to loopback so additional BW
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// can be reclaimed. Notice, LS don't support bulk transfer and
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// also doesn't support BW reclamation.
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//
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Uhc->SyncIntQh = UhciCreateQh (Uhc, 1);
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Uhc->CtrlQh = UhciCreateQh (Uhc, 1);
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Uhc->BulkQh = UhciCreateQh (Uhc, 1);
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if ((Uhc->SyncIntQh == NULL) || (Uhc->CtrlQh == NULL) || (Uhc->BulkQh == NULL)) {
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Uhc->PciIo->Unmap (Uhc->PciIo, Mapping);
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Status = EFI_OUT_OF_RESOURCES;
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goto ON_ERROR;
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}
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//
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// +-------------+
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// | |
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// Link the three together: SyncIntQh->CtrlQh->BulkQh <---------+
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// Each frame entry is linked to this sequence of QH. These QH
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// will remain on the schedul, never got removed
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//
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PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_HW));
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Uhc->SyncIntQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
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Uhc->SyncIntQh->NextQh = Uhc->CtrlQh;
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PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_HW));
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Uhc->CtrlQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
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Uhc->CtrlQh->NextQh = Uhc->BulkQh;
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//
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// Some old platform such as Intel's Tiger 4 has a difficult time
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// in supporting the full speed bandwidth reclamation in the previous
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// mentioned form. Most new platforms don't suffer it.
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//
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Uhc->BulkQh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
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Uhc->BulkQh->NextQh = NULL;
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Uhc->FrameBaseHostAddr = AllocateZeroPool (4096);
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if (Uhc->FrameBaseHostAddr == NULL) {
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Status = EFI_OUT_OF_RESOURCES;
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goto ON_ERROR;
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}
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PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_HW));
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for (Index = 0; Index < UHCI_FRAME_NUM; Index++) {
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Uhc->FrameBase[Index] = QH_HLINK (PhyAddr, FALSE);
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Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Uhc->SyncIntQh;
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}
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return EFI_SUCCESS;
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ON_ERROR:
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if (Uhc->SyncIntQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_SW));
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}
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if (Uhc->CtrlQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_SW));
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}
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if (Uhc->BulkQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_SW));
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}
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Uhc->PciIo->FreeBuffer (Uhc->PciIo, Pages, Buffer);
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return Status;
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}
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/**
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Destory FrameList buffer.
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@param Uhc The UHCI device.
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**/
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VOID
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UhciDestoryFrameList (
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IN USB_HC_DEV *Uhc
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)
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{
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//
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// Unmap the common buffer for framelist entry,
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// and free the common buffer.
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// Uhci's frame list occupy 4k memory.
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//
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Uhc->PciIo->Unmap (Uhc->PciIo, Uhc->FrameMapping);
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Uhc->PciIo->FreeBuffer (
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Uhc->PciIo,
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EFI_SIZE_TO_PAGES (4096),
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(VOID *) Uhc->FrameBase
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);
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if (Uhc->FrameBaseHostAddr != NULL) {
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FreePool (Uhc->FrameBaseHostAddr);
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}
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if (Uhc->SyncIntQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->SyncIntQh, sizeof (UHCI_QH_SW));
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}
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if (Uhc->CtrlQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->CtrlQh, sizeof (UHCI_QH_SW));
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}
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if (Uhc->BulkQh != NULL) {
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UsbHcFreeMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_SW));
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}
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Uhc->FrameBase = NULL;
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Uhc->FrameBaseHostAddr = NULL;
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Uhc->SyncIntQh = NULL;
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Uhc->CtrlQh = NULL;
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Uhc->BulkQh = NULL;
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}
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/**
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Convert the poll rate to the maxium 2^n that is smaller
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than Interval.
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@param Interval The poll rate to convert.
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@return The converted poll rate.
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**/
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UINTN
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UhciConvertPollRate (
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IN UINTN Interval
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)
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{
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UINTN BitCount;
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ASSERT (Interval != 0);
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//
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// Find the index (1 based) of the highest non-zero bit
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//
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BitCount = 0;
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while (Interval != 0) {
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Interval >>= 1;
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BitCount++;
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}
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return (UINTN)1 << (BitCount - 1);
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}
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/**
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Link a queue head (for asynchronous interrupt transfer) to
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the frame list.
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@param Uhc The UHCI device.
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@param Qh The queue head to link into.
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**/
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VOID
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UhciLinkQhToFrameList (
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USB_HC_DEV *Uhc,
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UHCI_QH_SW *Qh
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)
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{
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UINTN Index;
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UHCI_QH_SW *Prev;
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UHCI_QH_SW *Next;
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EFI_PHYSICAL_ADDRESS PhyAddr;
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EFI_PHYSICAL_ADDRESS QhPciAddr;
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ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
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QhPciAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Qh, sizeof (UHCI_QH_HW));
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for (Index = 0; Index < UHCI_FRAME_NUM; Index += Qh->Interval) {
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//
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// First QH can't be NULL because we always keep static queue
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// heads on the frame list
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//
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ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
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Next = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
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Prev = NULL;
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//
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// Now, insert the queue head (Qh) into this frame:
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// 1. Find a queue head with the same poll interval, just insert
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// Qh after this queue head, then we are done.
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//
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// 2. Find the position to insert the queue head into:
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// Previous head's interval is bigger than Qh's
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// Next head's interval is less than Qh's
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// Then, insert the Qh between then
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//
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// This method is very much the same as that used by EHCI.
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// Because each QH's interval is round down to 2^n, poll
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// rate is correct.
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//
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while (Next->Interval > Qh->Interval) {
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Prev = Next;
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Next = Next->NextQh;
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ASSERT (Next != NULL);
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}
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//
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// The entry may have been linked into the frame by early insertation.
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// For example: if insert a Qh with Qh.Interval == 4, and there is a Qh
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// with Qh.Interval == 8 on the frame. If so, we are done with this frame.
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// It isn't necessary to compare all the QH with the same interval to
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// Qh. This is because if there is other QH with the same interval, Qh
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// should has been inserted after that at FrameBase[0] and at FrameBase[0] it is
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// impossible (Next == Qh)
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//
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if (Next == Qh) {
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continue;
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}
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if (Next->Interval == Qh->Interval) {
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//
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// If there is a QH with the same interval, it locates at
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// FrameBase[0], and we can simply insert it after this QH. We
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// are all done.
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//
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ASSERT ((Index == 0) && (Qh->NextQh == NULL));
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Prev = Next;
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Next = Next->NextQh;
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Qh->NextQh = Next;
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Prev->NextQh = Qh;
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Qh->QhHw.HorizonLink = Prev->QhHw.HorizonLink;
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Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
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break;
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}
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//
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// OK, find the right position, insert it in. If Qh's next
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// link has already been set, it is in position. This is
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// guarranted by 2^n polling interval.
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//
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if (Qh->NextQh == NULL) {
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Qh->NextQh = Next;
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PhyAddr = UsbHcGetPciAddressForHostMem (Uhc->MemPool, Next, sizeof (UHCI_QH_HW));
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Qh->QhHw.HorizonLink = QH_HLINK (PhyAddr, FALSE);
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}
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if (Prev == NULL) {
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Uhc->FrameBase[Index] = QH_HLINK (QhPciAddr, FALSE);
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Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh;
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} else {
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Prev->NextQh = Qh;
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Prev->QhHw.HorizonLink = QH_HLINK (QhPciAddr, FALSE);
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}
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}
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}
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/**
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Unlink QH from the frame list is easier: find all
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the precedence node, and pointer there next to QhSw's
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next.
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@param Uhc The UHCI device.
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@param Qh The queue head to unlink.
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**/
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VOID
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UhciUnlinkQhFromFrameList (
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USB_HC_DEV *Uhc,
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UHCI_QH_SW *Qh
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)
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{
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UINTN Index;
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UHCI_QH_SW *Prev;
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UHCI_QH_SW *This;
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ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));
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for (Index = 0; Index < UHCI_FRAME_NUM; Index += Qh->Interval) {
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//
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// Frame link can't be NULL because we always keep static
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// queue heads on the frame list
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//
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ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));
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This = (UHCI_QH_SW*)(UINTN)Uhc->FrameBaseHostAddr[Index];
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Prev = NULL;
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//
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// Walk through the frame's QH list to find the
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// queue head to remove
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//
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while ((This != NULL) && (This != Qh)) {
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Prev = This;
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This = This->NextQh;
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}
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//
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// Qh may have already been unlinked from this frame
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// by early action.
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//
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if (This == NULL) {
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continue;
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}
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if (Prev == NULL) {
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//
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// Qh is the first entry in the frame
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//
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Uhc->FrameBase[Index] = Qh->QhHw.HorizonLink;
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Uhc->FrameBaseHostAddr[Index] = (UINT32)(UINTN)Qh->NextQh;
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} else {
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Prev->NextQh = Qh->NextQh;
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Prev->QhHw.HorizonLink = Qh->QhHw.HorizonLink;
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}
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}
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}
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/**
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Check TDs Results.
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@param Uhc This UHCI device.
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@param Td UHCI_TD_SW to check.
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@param IsLow Is Low Speed Device.
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@param QhResult Return the result of this TD list.
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@return Whether the TD's result is finialized.
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**/
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BOOLEAN
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UhciCheckTdStatus (
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IN USB_HC_DEV *Uhc,
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IN UHCI_TD_SW *Td,
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IN BOOLEAN IsLow,
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OUT UHCI_QH_RESULT *QhResult
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)
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{
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UINTN Len;
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UINT8 State;
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UHCI_TD_HW *TdHw;
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BOOLEAN Finished;
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Finished = TRUE;
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//
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// Initialize the data toggle to that of the first
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// TD. The next toggle to use is either:
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// 1. first TD's toggle if no TD is executed OK
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// 2. the next toggle of last executed-OK TD
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//
|
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QhResult->Result = EFI_USB_NOERROR;
|
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QhResult->NextToggle = (UINT8)Td->TdHw.DataToggle;
|
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QhResult->Complete = 0;
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|
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while (Td != NULL) {
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TdHw = &Td->TdHw;
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State = (UINT8)TdHw->Status;
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|
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//
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// UHCI will set STALLED bit when it abort the execution
|
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// of TD list. There are several reasons:
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// 1. BABBLE error happened
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// 2. Received a STALL response
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// 3. Error count decreased to zero.
|
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//
|
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// It also set CRC/Timeout/NAK/Buffer Error/BitStuff Error
|
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// bits when corresponding conditions happen. But these
|
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// conditions are not deadly, that is a TD can successfully
|
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// completes even these bits are set. But it is likely that
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// upper layer won't distinguish these condtions. So, only
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// set these bits when TD is actually halted.
|
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//
|
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if ((State & USBTD_STALLED) != 0) {
|
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if ((State & USBTD_BABBLE) != 0) {
|
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QhResult->Result |= EFI_USB_ERR_BABBLE;
|
|
|
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} else if (TdHw->ErrorCount != 0) {
|
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QhResult->Result |= EFI_USB_ERR_STALL;
|
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}
|
|
|
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if ((State & USBTD_CRC) != 0) {
|
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QhResult->Result |= EFI_USB_ERR_CRC;
|
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}
|
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|
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if ((State & USBTD_BUFFERR) != 0) {
|
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QhResult->Result |= EFI_USB_ERR_BUFFER;
|
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}
|
|
|
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if ((Td->TdHw.Status & USBTD_BITSTUFF) != 0) {
|
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QhResult->Result |= EFI_USB_ERR_BITSTUFF;
|
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}
|
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|
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if (TdHw->ErrorCount == 0) {
|
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QhResult->Result |= EFI_USB_ERR_TIMEOUT;
|
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}
|
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|
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Finished = TRUE;
|
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goto ON_EXIT;
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|
|
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} else if ((State & USBTD_ACTIVE) != 0) {
|
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//
|
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// The TD is still active, no need to check further.
|
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//
|
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QhResult->Result |= EFI_USB_ERR_NOTEXECUTE;
|
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|
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Finished = FALSE;
|
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goto ON_EXIT;
|
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|
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} else {
|
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//
|
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// Update the next data toggle, it is always the
|
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// next to the last known-good TD's data toggle if
|
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// any TD is executed OK
|
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//
|
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QhResult->NextToggle = (UINT8) (1 - (UINT8)TdHw->DataToggle);
|
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|
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//
|
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// This TD is finished OK or met short packet read. Update the
|
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// transfer length if it isn't a SETUP.
|
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//
|
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Len = (TdHw->ActualLen + 1) & 0x7FF;
|
|
|
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if (TdHw->PidCode != SETUP_PACKET_ID) {
|
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QhResult->Complete += Len;
|
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}
|
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|
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//
|
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// Short packet condition for full speed input TD, also
|
|
// terminate the transfer
|
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//
|
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if (!IsLow && (TdHw->ShortPacket == 1) && (Len < Td->DataLen)) {
|
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DEBUG ((EFI_D_INFO, "UhciCheckTdStatus: short packet read occured\n"));
|
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|
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Finished = TRUE;
|
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goto ON_EXIT;
|
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}
|
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}
|
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|
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Td = Td->NextTd;
|
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}
|
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|
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ON_EXIT:
|
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//
|
|
// Check whether HC is halted. Don't move this up. It must be
|
|
// called after data toggle is successfully updated.
|
|
//
|
|
if (!UhciIsHcWorking (Uhc->PciIo)) {
|
|
QhResult->Result |= EFI_USB_ERR_SYSTEM;
|
|
Finished = TRUE;
|
|
}
|
|
|
|
if (Finished) {
|
|
Uhc->PciIo->Flush (Uhc->PciIo);
|
|
}
|
|
|
|
UhciAckAllInterrupt (Uhc);
|
|
return Finished;
|
|
}
|
|
|
|
|
|
/**
|
|
Check the result of the transfer.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param Qh The queue head of the transfer.
|
|
@param Td The first TDs of the transfer.
|
|
@param TimeOut TimeOut value in milliseconds.
|
|
@param IsLow Is Low Speed Device.
|
|
@param QhResult The variable to return result.
|
|
|
|
@retval EFI_SUCCESS The transfer finished with success.
|
|
@retval EFI_DEVICE_ERROR Transfer failed.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
UhciExecuteTransfer (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UHCI_QH_SW *Qh,
|
|
IN UHCI_TD_SW *Td,
|
|
IN UINTN TimeOut,
|
|
IN BOOLEAN IsLow,
|
|
OUT UHCI_QH_RESULT *QhResult
|
|
)
|
|
{
|
|
UINTN Index;
|
|
UINTN Delay;
|
|
BOOLEAN Finished;
|
|
EFI_STATUS Status;
|
|
|
|
Finished = FALSE;
|
|
Status = EFI_SUCCESS;
|
|
Delay = (TimeOut * UHC_1_MILLISECOND / UHC_SYNC_POLL_INTERVAL) + 1;
|
|
|
|
for (Index = 0; Index < Delay; Index++) {
|
|
Finished = UhciCheckTdStatus (Uhc, Td, IsLow, QhResult);
|
|
|
|
//
|
|
// Transfer is OK or some error occured (TD inactive)
|
|
//
|
|
if (Finished) {
|
|
break;
|
|
}
|
|
|
|
gBS->Stall (UHC_SYNC_POLL_INTERVAL);
|
|
}
|
|
|
|
if (!Finished) {
|
|
DEBUG ((EFI_D_ERROR, "UhciExecuteTransfer: execution not finished for %dms\n", (UINT32)TimeOut));
|
|
UhciDumpQh (Qh);
|
|
UhciDumpTds (Td);
|
|
|
|
Status = EFI_TIMEOUT;
|
|
|
|
} else if (QhResult->Result != EFI_USB_NOERROR) {
|
|
DEBUG ((EFI_D_ERROR, "UhciExecuteTransfer: execution failed with result %x\n", QhResult->Result));
|
|
UhciDumpQh (Qh);
|
|
UhciDumpTds (Td);
|
|
|
|
Status = EFI_DEVICE_ERROR;
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
|
|
/**
|
|
Update Async Request, QH and TDs.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param AsyncReq The UHCI asynchronous transfer to update.
|
|
@param Result Transfer reslut.
|
|
@param NextToggle The toggle of next data.
|
|
|
|
**/
|
|
VOID
|
|
UhciUpdateAsyncReq (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UHCI_ASYNC_REQUEST *AsyncReq,
|
|
IN UINT32 Result,
|
|
IN UINT32 NextToggle
|
|
)
|
|
{
|
|
UHCI_QH_SW *Qh;
|
|
UHCI_TD_SW *FirstTd;
|
|
UHCI_TD_SW *Td;
|
|
|
|
Qh = AsyncReq->QhSw;
|
|
FirstTd = AsyncReq->FirstTd;
|
|
|
|
if (Result == EFI_USB_NOERROR) {
|
|
//
|
|
// The last transfer succeeds. Then we need to update
|
|
// the Qh and Td for next round of transfer.
|
|
// 1. Update the TD's data toggle
|
|
// 2. Activate all the TDs
|
|
// 3. Link the TD to the queue head again since during
|
|
// execution, queue head's TD pointer is changed by
|
|
// hardware.
|
|
//
|
|
for (Td = FirstTd; Td != NULL; Td = Td->NextTd) {
|
|
Td->TdHw.DataToggle = NextToggle;
|
|
NextToggle ^= 1;
|
|
Td->TdHw.Status |= USBTD_ACTIVE;
|
|
}
|
|
|
|
UhciLinkTdToQh (Uhc, Qh, FirstTd);
|
|
return ;
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
Create Async Request node, and Link to List.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param Qh The queue head of the transfer.
|
|
@param FirstTd First TD of the transfer.
|
|
@param DevAddr Device Address.
|
|
@param EndPoint EndPoint Address.
|
|
@param DataLen Data length.
|
|
@param Interval Polling Interval when inserted to frame list.
|
|
@param Data Data buffer, unmapped.
|
|
@param Callback Callback after interrupt transfeer.
|
|
@param Context Callback Context passed as function parameter.
|
|
@param IsLow Is Low Speed.
|
|
|
|
@retval EFI_SUCCESS An asynchronous transfer is created.
|
|
@retval EFI_INVALID_PARAMETER Paremeter is error.
|
|
@retval EFI_OUT_OF_RESOURCES Failed because of resource shortage.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
UhciCreateAsyncReq (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UHCI_QH_SW *Qh,
|
|
IN UHCI_TD_SW *FirstTd,
|
|
IN UINT8 DevAddr,
|
|
IN UINT8 EndPoint,
|
|
IN UINTN DataLen,
|
|
IN UINTN Interval,
|
|
IN UINT8 *Data,
|
|
IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
|
|
IN VOID *Context,
|
|
IN BOOLEAN IsLow
|
|
)
|
|
{
|
|
UHCI_ASYNC_REQUEST *AsyncReq;
|
|
|
|
AsyncReq = AllocatePool (sizeof (UHCI_ASYNC_REQUEST));
|
|
|
|
if (AsyncReq == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// Fill Request field. Data is allocated host memory, not mapped
|
|
//
|
|
AsyncReq->Signature = UHCI_ASYNC_INT_SIGNATURE;
|
|
AsyncReq->DevAddr = DevAddr;
|
|
AsyncReq->EndPoint = EndPoint;
|
|
AsyncReq->DataLen = DataLen;
|
|
AsyncReq->Interval = UhciConvertPollRate(Interval);
|
|
AsyncReq->Data = Data;
|
|
AsyncReq->Callback = Callback;
|
|
AsyncReq->Context = Context;
|
|
AsyncReq->QhSw = Qh;
|
|
AsyncReq->FirstTd = FirstTd;
|
|
AsyncReq->IsLow = IsLow;
|
|
|
|
//
|
|
// Insert the new interrupt transfer to the head of the list.
|
|
// The interrupt transfer's monitor function scans the whole
|
|
// list from head to tail. The new interrupt transfer MUST be
|
|
// added to the head of the list.
|
|
//
|
|
InsertHeadList (&(Uhc->AsyncIntList), &(AsyncReq->Link));
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
|
|
/**
|
|
Free an asynchronous request's resource such as memory.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param AsyncReq The asynchronous request to free.
|
|
|
|
**/
|
|
VOID
|
|
UhciFreeAsyncReq (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UHCI_ASYNC_REQUEST *AsyncReq
|
|
)
|
|
{
|
|
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
|
|
|
|
UhciDestoryTds (Uhc, AsyncReq->FirstTd);
|
|
UsbHcFreeMem (Uhc->MemPool, AsyncReq->QhSw, sizeof (UHCI_QH_SW));
|
|
|
|
if (AsyncReq->Data != NULL) {
|
|
UsbHcFreeMem (Uhc->MemPool, AsyncReq->Data, AsyncReq->DataLen);
|
|
}
|
|
|
|
gBS->FreePool (AsyncReq);
|
|
}
|
|
|
|
|
|
/**
|
|
Unlink an asynchronous request's from UHC's asynchronus list.
|
|
also remove the queue head from the frame list. If FreeNow,
|
|
release its resource also. Otherwise, add the request to the
|
|
UHC's recycle list to wait for a while before release the memory.
|
|
Until then, hardware won't hold point to the request.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param AsyncReq The asynchronous request to free.
|
|
@param FreeNow If TRUE, free the resource immediately, otherwise
|
|
add the request to recycle wait list.
|
|
|
|
**/
|
|
VOID
|
|
UhciUnlinkAsyncReq (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UHCI_ASYNC_REQUEST *AsyncReq,
|
|
IN BOOLEAN FreeNow
|
|
)
|
|
{
|
|
ASSERT ((Uhc != NULL) && (AsyncReq != NULL));
|
|
|
|
RemoveEntryList (&(AsyncReq->Link));
|
|
UhciUnlinkQhFromFrameList (Uhc, AsyncReq->QhSw);
|
|
|
|
if (FreeNow) {
|
|
UhciFreeAsyncReq (Uhc, AsyncReq);
|
|
} else {
|
|
//
|
|
// To sychronize with hardware, mark the queue head as inactive
|
|
// then add AsyncReq to UHC's recycle list
|
|
//
|
|
AsyncReq->QhSw->QhHw.VerticalLink = QH_VLINK (NULL, TRUE);
|
|
AsyncReq->Recycle = Uhc->RecycleWait;
|
|
Uhc->RecycleWait = AsyncReq;
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
Delete Async Interrupt QH and TDs.
|
|
|
|
@param Uhc The UHCI device.
|
|
@param DevAddr Device Address.
|
|
@param EndPoint EndPoint Address.
|
|
@param Toggle The next data toggle to use.
|
|
|
|
@retval EFI_SUCCESS The request is deleted.
|
|
@retval EFI_INVALID_PARAMETER Paremeter is error.
|
|
@retval EFI_NOT_FOUND The asynchronous isn't found.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
UhciRemoveAsyncReq (
|
|
IN USB_HC_DEV *Uhc,
|
|
IN UINT8 DevAddr,
|
|
IN UINT8 EndPoint,
|
|
OUT UINT8 *Toggle
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UHCI_ASYNC_REQUEST *AsyncReq;
|
|
UHCI_QH_RESULT QhResult;
|
|
LIST_ENTRY *Link;
|
|
BOOLEAN Found;
|
|
|
|
Status = EFI_SUCCESS;
|
|
|
|
//
|
|
// If no asynchronous interrupt transaction exists
|
|
//
|
|
if (IsListEmpty (&(Uhc->AsyncIntList))) {
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Find the asynchronous transfer to this device/endpoint pair
|
|
//
|
|
Found = FALSE;
|
|
Link = Uhc->AsyncIntList.ForwardLink;
|
|
|
|
do {
|
|
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
|
|
Link = Link->ForwardLink;
|
|
|
|
if ((AsyncReq->DevAddr == DevAddr) && (AsyncReq->EndPoint == EndPoint)) {
|
|
Found = TRUE;
|
|
break;
|
|
}
|
|
|
|
} while (Link != &(Uhc->AsyncIntList));
|
|
|
|
if (!Found) {
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// Check the result of the async transfer then update it
|
|
// to get the next data toggle to use.
|
|
//
|
|
UhciCheckTdStatus (Uhc, AsyncReq->FirstTd, AsyncReq->IsLow, &QhResult);
|
|
*Toggle = QhResult.NextToggle;
|
|
|
|
//
|
|
// Don't release the request now, keep it to synchronize with hardware.
|
|
//
|
|
UhciUnlinkAsyncReq (Uhc, AsyncReq, FALSE);
|
|
return Status;
|
|
}
|
|
|
|
|
|
/**
|
|
Recycle the asynchronouse request. When a queue head
|
|
is unlinked from frame list, host controller hardware
|
|
may still hold a cached pointer to it. To synchronize
|
|
with hardware, the request is released in two steps:
|
|
first it is linked to the UHC's RecycleWait list. At
|
|
the next time UhciMonitorAsyncReqList is fired, it is
|
|
moved to UHC's Recylelist. Then, at another timer
|
|
activation, all the requests on Recycle list is freed.
|
|
This guarrantes that each unlink queue head keeps
|
|
existing for at least 50ms, far enough for the hardware
|
|
to clear its cache.
|
|
|
|
@param Uhc The UHCI device.
|
|
|
|
**/
|
|
VOID
|
|
UhciRecycleAsyncReq (
|
|
IN USB_HC_DEV *Uhc
|
|
)
|
|
{
|
|
UHCI_ASYNC_REQUEST *Req;
|
|
UHCI_ASYNC_REQUEST *Next;
|
|
|
|
Req = Uhc->Recycle;
|
|
|
|
while (Req != NULL) {
|
|
Next = Req->Recycle;
|
|
UhciFreeAsyncReq (Uhc, Req);
|
|
Req = Next;
|
|
}
|
|
|
|
Uhc->Recycle = Uhc->RecycleWait;
|
|
Uhc->RecycleWait = NULL;
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
Release all the asynchronous transfers on the lsit.
|
|
|
|
@param Uhc The UHCI device.
|
|
|
|
**/
|
|
VOID
|
|
UhciFreeAllAsyncReq (
|
|
IN USB_HC_DEV *Uhc
|
|
)
|
|
{
|
|
LIST_ENTRY *Head;
|
|
UHCI_ASYNC_REQUEST *AsyncReq;
|
|
|
|
//
|
|
// Call UhciRecycleAsyncReq twice. The requests on Recycle
|
|
// will be released at the first call; The requests on
|
|
// RecycleWait will be released at the second call.
|
|
//
|
|
UhciRecycleAsyncReq (Uhc);
|
|
UhciRecycleAsyncReq (Uhc);
|
|
|
|
Head = &(Uhc->AsyncIntList);
|
|
|
|
if (IsListEmpty (Head)) {
|
|
return;
|
|
}
|
|
|
|
while (!IsListEmpty (Head)) {
|
|
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Head->ForwardLink);
|
|
UhciUnlinkAsyncReq (Uhc, AsyncReq, TRUE);
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
Interrupt transfer periodic check handler.
|
|
|
|
@param Event The event of the time.
|
|
@param Context Context of the event, pointer to USB_HC_DEV.
|
|
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
UhciMonitorAsyncReqList (
|
|
IN EFI_EVENT Event,
|
|
IN VOID *Context
|
|
)
|
|
{
|
|
UHCI_ASYNC_REQUEST *AsyncReq;
|
|
LIST_ENTRY *Link;
|
|
USB_HC_DEV *Uhc;
|
|
VOID *Data;
|
|
BOOLEAN Finished;
|
|
UHCI_QH_RESULT QhResult;
|
|
|
|
Uhc = (USB_HC_DEV *) Context;
|
|
|
|
//
|
|
// Recycle the asynchronous requests expired, and promote
|
|
// requests waiting to be recycled the next time when this
|
|
// timer expires
|
|
//
|
|
UhciRecycleAsyncReq (Uhc);
|
|
|
|
if (IsListEmpty (&(Uhc->AsyncIntList))) {
|
|
return ;
|
|
}
|
|
|
|
//
|
|
// This loop must be delete safe
|
|
//
|
|
Link = Uhc->AsyncIntList.ForwardLink;
|
|
|
|
do {
|
|
AsyncReq = UHCI_ASYNC_INT_FROM_LINK (Link);
|
|
Link = Link->ForwardLink;
|
|
|
|
Finished = UhciCheckTdStatus (Uhc, AsyncReq->FirstTd, AsyncReq->IsLow, &QhResult);
|
|
|
|
if (!Finished) {
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// Copy the data to temporary buffer if there are some
|
|
// data transferred. We may have zero-length packet
|
|
//
|
|
Data = NULL;
|
|
|
|
if (QhResult.Complete != 0) {
|
|
Data = AllocatePool (QhResult.Complete);
|
|
|
|
if (Data == NULL) {
|
|
return ;
|
|
}
|
|
|
|
CopyMem (Data, AsyncReq->FirstTd->Data, QhResult.Complete);
|
|
}
|
|
|
|
UhciUpdateAsyncReq (Uhc, AsyncReq, QhResult.Result, QhResult.NextToggle);
|
|
|
|
//
|
|
// Now, either transfer is SUCCESS or met errors since
|
|
// we have skipped to next transfer earlier if current
|
|
// transfer is still active.
|
|
//
|
|
if (QhResult.Result == EFI_USB_NOERROR) {
|
|
AsyncReq->Callback (Data, QhResult.Complete, AsyncReq->Context, QhResult.Result);
|
|
} else {
|
|
//
|
|
// Leave error recovery to its related device driver.
|
|
// A common case of the error recovery is to re-submit
|
|
// the interrupt transfer. When an interrupt transfer
|
|
// is re-submitted, its position in the linked list is
|
|
// changed. It is inserted to the head of the linked
|
|
// list, while this function scans the whole list from
|
|
// head to tail. Thus, the re-submitted interrupt transfer's
|
|
// callback function will not be called again in this round.
|
|
//
|
|
AsyncReq->Callback (NULL, 0, AsyncReq->Context, QhResult.Result);
|
|
}
|
|
|
|
if (Data != NULL) {
|
|
gBS->FreePool (Data);
|
|
}
|
|
} while (Link != &(Uhc->AsyncIntList));
|
|
}
|