audk/UefiCpuPkg/PiSmmCpuDxeSmm/X64
Leo Duran 241f914975 UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entriees are created or modified.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-01 12:53:03 +08:00
..
MpFuncs.S
MpFuncs.asm
MpFuncs.nasm UefiCpuPkg PiSmmCpuDxeSmm: Update X64/MpFuncs.nasm 2016-06-28 09:52:16 +08:00
PageTbl.c UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask 2017-03-01 12:53:03 +08:00
Semaphore.c
SmiEntry.S UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure 2016-12-16 08:27:59 +08:00
SmiEntry.asm UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure 2016-12-16 08:27:59 +08:00
SmiEntry.nasm UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. 2016-11-17 16:30:07 +08:00
SmiException.S UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRR field from PSD 2016-12-06 23:34:16 -08:00
SmiException.asm UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRR field from PSD 2016-12-06 23:34:16 -08:00
SmiException.nasm UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRR field from PSD 2016-12-06 23:34:16 -08:00
SmmFuncsArch.c UefiCpuPkg/PiSmmCpu: Fixed #double fault on #page fault. 2016-12-07 13:13:55 +08:00
SmmInit.S
SmmInit.asm
SmmInit.nasm UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASM 2016-06-28 09:52:18 +08:00
SmmProfileArch.c UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask 2017-03-01 12:53:03 +08:00
SmmProfileArch.h