mirror of https://github.com/acidanthera/audk.git
122 lines
4.3 KiB
C
122 lines
4.3 KiB
C
/** @file
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Support for the PCI Express 6.0 standard.
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This header file may not define all structures. Please extend as required.
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Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef PCIEXPRESS60_H_
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#define PCIEXPRESS60_H_
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#include <IndustryStandard/PciExpress50.h>
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/// The Physical Layer PCI Express Extended Capability definitions.
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///
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/// Based on section 7.7.7 of PCI Express Base Specification 6.0.
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///@{
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
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// Register offsets from Physical Layer PCI-E Ext Cap Header
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
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#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
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#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
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#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 Reserved : 32; // Reserved bit 0:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
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typedef union {
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struct {
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UINT32 Reserved : 32; // Reserved bit 0:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
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typedef union {
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struct {
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UINT32 EqualizationComplete : 1; // bit 0
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UINT32 EqualizationPhase1Success : 1; // bit 1
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UINT32 EqualizationPhase2Success : 1; // bit 2
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UINT32 EqualizationPhase3Success : 1; // bit 3
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UINT32 LinkEqualizationRequest : 1; // bit 4
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UINT32 TransmitterPrecodingOn : 1; // bit 5
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UINT32 TransmitterPrecodeRequest : 1; // bit 6
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UINT32 NoEqualizationNeededRcvd : 1; // bit 7
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UINT32 Reserved : 24; // Reserved bit 8:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
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typedef union {
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struct {
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UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
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UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
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} Bits;
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UINT8 Uint8;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
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typedef struct {
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PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
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} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
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///@}
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typedef union {
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struct {
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UINT32 DmwrRequestRouting : 1; // bit 0
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UINT32 FourteenBitTagCompleter : 1; // bit 1
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UINT32 FourteenBitTagRequester : 1; // bit 2
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UINT32 ReceiverL0p : 1; // bit 3
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UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
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UINT32 RetimerL0pExit : 3; // bit 7..9
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UINT32 Reserved : 22; // bit 10..31
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CAPABILITY3;
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typedef union {
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struct {
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UINT32 DmwrRequesterEnable : 1; // bit 0
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UINT32 DmwrEgressBlocking : 1; // bit 1
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UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
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UINT32 L0pEnable : 1; // bit 3
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UINT32 TargetLinkWidth : 3; // bit 4..6
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UINT32 Reserved : 25; // bit 7..31
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CONTROL3;
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typedef union {
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struct {
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UINT32 InitialLinkWidth : 3; // bit 0..2
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UINT32 SegmentCaptured : 1; // bit 3
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UINT32 RemoteL0pSupported : 1; // bit 4
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UINT32 Reserved : 27; // bit 5..31
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_STATUS3;
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#pragma pack()
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#endif
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