mirror of https://github.com/acidanthera/audk.git
705c3469b5
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add the RISC-V instance of the TimerLib. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com> |
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BaseRiscV64CpuExceptionHandlerLib | ||
BaseRiscV64CpuTimerLib | ||
BaseUefiCpuLib | ||
BaseXApicLib | ||
BaseXApicX2ApicLib | ||
CcExitLibNull | ||
CpuCacheInfoLib | ||
CpuCommonFeaturesLib | ||
CpuExceptionHandlerLib | ||
CpuPageTableLib | ||
CpuTimerLib | ||
MicrocodeLib | ||
MpInitLib | ||
MpInitLibUp | ||
MtrrLib | ||
PlatformSecLibNull | ||
RegisterCpuFeaturesLib | ||
SecPeiDxeTimerLibUefiCpu | ||
SmmCpuFeaturesLib | ||
SmmCpuPlatformHookLibNull | ||
SmmCpuRendezvousLib |