mirror of https://github.com/acidanthera/audk.git
516 lines
16 KiB
C
516 lines
16 KiB
C
/** @file CpuDxe.c
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CPU DXE Module to produce CPU ARCH Protocol.
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Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuDxe.h"
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#include "CpuMp.h"
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#include <Guid/IdleLoopEvent.h>
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#include <Library/CpuMmuLib.h>
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#include <Library/TimerLib.h>
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#include <Register/LoongArch64/Csr.h>
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UINT64 mTimerPeriod = 0;
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/**
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IPI Interrupt Handler.
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@param InterruptType The type of interrupt that occurred
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@param SystemContext A pointer to the system context when the interrupt occurred
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**/
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VOID
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EFIAPI
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IpiInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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);
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//
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// Globals used to initialize the protocol
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//
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EFI_HANDLE mCpuHandle = NULL;
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EFI_CPU_ARCH_PROTOCOL gCpu = {
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CpuFlushCpuDataCache,
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CpuEnableInterrupt,
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CpuDisableInterrupt,
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CpuGetInterruptState,
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CpuInit,
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CpuRegisterInterruptHandler,
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CpuGetTimerValue,
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CpuSetMemoryAttributes,
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0, // NumberOfTimers
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4, // DmaBufferAlignment
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};
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/**
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This function flushes the range of addresses from Start to Start+Length
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from the processor's data cache. If Start is not aligned to a cache line
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boundary, then the bytes before Start to the preceding cache line boundary
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are also flushed. If Start+Length is not aligned to a cache line boundary,
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then the bytes past Start+Length to the end of the next cache line boundary
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are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
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supported. If the data cache is fully coherent with all DMA operations, then
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this function can just return EFI_SUCCESS. If the processor does not support
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flushing a range of the data cache, then the entire data cache can be flushed.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param Start The beginning physical address to flush from the processor's data
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cache.
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@param Length The number of bytes to flush from the processor's data cache. This
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function may flush more bytes than Length specifies depending upon
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the granularity of the flush operation that the processor supports.
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@param FlushType Specifies the type of flush operation to perform.
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@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
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the processor's data cache.
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@retval EFI_INVALID_PARAMETER The processor does not support the cache flush type specified
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by FlushType.
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**/
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EFI_STATUS
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EFIAPI
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CpuFlushCpuDataCache (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS Start,
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IN UINT64 Length,
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IN EFI_CPU_FLUSH_TYPE FlushType
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)
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{
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switch (FlushType) {
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case EfiCpuFlushTypeWriteBack:
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WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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case EfiCpuFlushTypeInvalidate:
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InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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case EfiCpuFlushTypeWriteBackInvalidate:
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WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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This function enables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are enabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuEnableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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)
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{
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EnableInterrupts ();
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return EFI_SUCCESS;
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}
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/**
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This function disables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are disabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuDisableInterrupt (
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IN EFI_CPU_ARCH_PROTOCOL *This
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)
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{
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DisableInterrupts ();
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return EFI_SUCCESS;
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}
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/**
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This function retrieves the processor's current interrupt state a returns it in
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State. If interrupts are currently enabled, then TRUE is returned. If interrupts
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are currently disabled, then FALSE is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param State A pointer to the processor's current interrupt state. Set to TRUE if
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interrupts are enabled and FALSE if interrupts are disabled.
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@retval EFI_SUCCESS The processor's current interrupt state was returned in State.
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@retval EFI_INVALID_PARAMETER State is NULL.
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**/
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EFI_STATUS
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EFIAPI
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CpuGetInterruptState (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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OUT BOOLEAN *State
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)
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{
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if (State == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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*State = GetInterruptState ();
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return EFI_SUCCESS;
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}
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/**
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This function generates an INIT on the processor. If this function succeeds, then the
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processor will be reset, and control will not be returned to the caller. If InitType is
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not supported by this processor, or the processor cannot programmatically generate an
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INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
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occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param InitType The type of processor INIT to perform.
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@retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
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@retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
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by this processor.
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@retval EFI_DEVICE_ERROR The processor INIT failed.
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**/
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EFI_STATUS
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EFIAPI
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CpuInit (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_CPU_INIT_TYPE InitType
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Registers a function to be called from the CPU interrupt handler.
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@param This Protocol instance structure
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@param InterruptType Defines which interrupt to hook. IA-32
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valid range is 0x00 through 0xFF
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@param InterruptHandler A pointer to a function of type
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EFI_CPU_INTERRUPT_HANDLER that is called
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when a processor interrupt occurs. A null
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pointer is an error condition.
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@retval EFI_SUCCESS If handler installed or uninstalled.
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@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
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for InterruptType was previously installed.
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@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
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InterruptType was not previously installed.
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@retval EFI_UNSUPPORTED The interrupt specified by InterruptType
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is not supported.
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**/
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EFI_STATUS
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EFIAPI
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CpuRegisterInterruptHandler (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
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)
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{
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return RegisterInterruptHandler (InterruptType, InterruptHandler);
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}
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/**
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Returns a timer value from one of the CPU's internal timers. There is no
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inherent time interval between ticks but is a function of the CPU frequency.
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@param This - Protocol instance structure.
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@param TimerIndex - Specifies which CPU timer is requested.
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@param TimerValue - Pointer to the returned timer value.
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@param TimerPeriod - A pointer to the amount of time that passes
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in femtoseconds (10-15) for each increment
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of TimerValue. If TimerValue does not
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increment at a predictable rate, then 0 is
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returned. The amount of time that has
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passed between two calls to GetTimerValue()
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can be calculated with the formula
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(TimerValue2 - TimerValue1) * TimerPeriod.
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This parameter is optional and may be NULL.
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@retval EFI_SUCCESS - If the CPU timer count was returned.
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@retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
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@retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
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@retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
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**/
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EFI_STATUS
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EFIAPI
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CpuGetTimerValue (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN UINT32 TimerIndex,
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OUT UINT64 *TimerValue,
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OUT UINT64 *TimerPeriod OPTIONAL
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)
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{
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UINT64 BeginValue;
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UINT64 EndValue;
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if (TimerValue == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if (TimerIndex != 0) {
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return EFI_INVALID_PARAMETER;
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}
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*TimerValue = AsmReadStableCounter ();
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if (TimerPeriod != NULL) {
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if (mTimerPeriod == 0) {
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//
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// Read time stamp counter before and after delay of 100 microseconds
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//
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BeginValue = AsmReadStableCounter ();
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MicroSecondDelay (100);
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EndValue = AsmReadStableCounter ();
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//
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// Calculate the actual frequency
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//
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mTimerPeriod = DivU64x64Remainder (
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MultU64x32 (
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1000 * 1000 * 1000,
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100
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),
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EndValue - BeginValue,
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NULL
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);
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}
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*TimerPeriod = mTimerPeriod;
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}
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return EFI_SUCCESS;
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}
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/**
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This function modifies the attributes for the memory region specified by BaseAddress and
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Length from their current attributes to the attributes specified by Attributes.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param BaseAddress The physical address that is the start address of a memory region.
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@param Length The size in bytes of the memory region.
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@param EfiAttributes The bit mask of attributes to set for the memory region.
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@retval EFI_SUCCESS The attributes were set for the memory region.
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@retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
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BaseAddress and Length cannot be modified.
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@retval EFI_INVALID_PARAMETER Length is zero.
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@retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
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the memory resource range.
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@retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
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resource range specified by BaseAddress and Length.
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The bit mask of attributes is not support for the memory resource
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range specified by BaseAddress and Length.
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**/
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EFI_STATUS
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EFIAPI
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CpuSetMemoryAttributes (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 EfiAttributes
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)
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{
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EFI_STATUS Status;
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UINTN PageTable;
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UINT64 PageWalkCfg;
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Status = EFI_SUCCESS;
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PageTable = CsrRead (LOONGARCH_CSR_PGDL);
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PageWalkCfg = ((UINT64)CsrRead (LOONGARCH_CSR_PWCTL1)) << 32 | CsrRead (LOONGARCH_CSR_PWCTL0);
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if ((BaseAddress & (EFI_PAGE_SIZE - 1)) != 0) {
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//
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// Minimum granularity is SIZE_4KB.
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//
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DEBUG ((
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DEBUG_INFO,
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"MemoryRegionMap(%lx, %lx, %lx, %lx, %lx): Minimum granularity is SIZE_4KB\n",
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&PageTable,
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PageWalkCfg,
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BaseAddress,
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Length,
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EfiAttributes
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));
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Status = EFI_UNSUPPORTED;
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return Status;
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}
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Status = MemoryRegionMap (
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&PageTable,
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PageWalkCfg,
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BaseAddress,
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Length,
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EfiAttributes,
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0x0
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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/**
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Callback function for idle events.
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@param Event Event whose notification function is being invoked.
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@param Context The pointer to the notification function's context,
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which is implementation-dependent.
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**/
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VOID
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EFIAPI
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IdleLoopEventCallback (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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CpuSleep ();
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}
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/**
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Refreshes the GCD Memory Space attributes according to Default Config
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This function refreshes the GCD Memory Space attributes according to DefaultConfig
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@retval EFI_SUCCESS Refresh GCD success.
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**/
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EFI_STATUS
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RefreshGcdMemoryAttributes (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT32 Index;
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UINTN NumberOfDescriptors;
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EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
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DEBUG ((DEBUG_PAGE, "RefreshGcdMemoryAttributes()\n"));
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//
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// Get the memory space map from GCD
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//
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MemorySpaceMap = NULL;
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Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
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if (EFI_ERROR (Status)) {
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DEBUG ((
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DEBUG_ERROR,
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"RefreshGcdMemoryAttributes - GetMemorySpaceMap() failed! Status: %r\n",
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Status
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));
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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for ( Index = 0; Index < NumberOfDescriptors; Index++ ) {
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//
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// If this is system memory, not a class resource like MMIO, and the capability
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// contains a Memory cacheability attributes and the attribute feature is set
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// to 0, we will set its attribute to the WriteBack memory of the LoongArch
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// architecture for the first time.
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//
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if (((MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeSystemMemory) &&
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MemorySpaceMap[Index].Capabilities & EFI_CACHE_ATTRIBUTE_MASK) &&
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(MemorySpaceMap[Index].Attributes == 0))
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{
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if (!(MemorySpaceMap[Index].Capabilities & EFI_MEMORY_WB)) {
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DEBUG ((
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DEBUG_WARN,
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"RefreshGcdMemoryAttributes - SystemMemory Capabilities should support EFI_MEMORY_WB ! \n"
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));
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}
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//
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// Refresh or Sync Gcd's memory attributes according to Default Paging (CACHE_CC)
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//
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gDS->SetMemorySpaceAttributes (
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MemorySpaceMap[Index].BaseAddress,
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MemorySpaceMap[Index].Length,
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(MemorySpaceMap[Index].Attributes & ~EFI_CACHE_ATTRIBUTE_MASK) |
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(MemorySpaceMap[Index].Capabilities & EFI_MEMORY_WB)
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);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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Initialize the state information for the CPU Architectural Protocol.
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@param ImageHandle Image handle this driver.
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@param SystemTable Pointer to the System Table.
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@retval EFI_SUCCESS Thread can be successfully created
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Cannot create the thread
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**/
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EFI_STATUS
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InitializeCpu (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT IdleLoopEvent;
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InitializeExceptions (&gCpu);
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Status = gBS->InstallMultipleProtocolInterfaces (
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&mCpuHandle,
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&gEfiCpuArchProtocolGuid,
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&gCpu,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Refresh GCD memory space map according to Default Paging.
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//
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RefreshGcdMemoryAttributes ();
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Status = gCpu.RegisterInterruptHandler (
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&gCpu,
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EXCEPT_LOONGARCH_INT_IPI,
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IpiInterruptHandler
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Setup a callback for idle events
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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IdleLoopEventCallback,
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NULL,
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&gIdleLoopEventGuid,
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&IdleLoopEvent
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);
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ASSERT_EFI_ERROR (Status);
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InitializeMpSupport ();
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return Status;
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}
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