mirror of https://github.com/acidanthera/audk.git
623 lines
17 KiB
C
623 lines
17 KiB
C
/**@file
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Platform PEI driver
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Ppi/MasterBootMode.h>
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#include <IndustryStandard/Pci22.h>
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#include <OvmfPlatforms.h>
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#include "Platform.h"
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#include "Cmos.h"
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EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
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{ EfiACPIMemoryNVS, 0x004 },
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{ EfiACPIReclaimMemory, 0x008 },
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{ EfiReservedMemoryType, 0x004 },
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{ EfiRuntimeServicesData, 0x024 },
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{ EfiRuntimeServicesCode, 0x030 },
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{ EfiBootServicesCode, 0x180 },
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{ EfiBootServicesData, 0xF00 },
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{ EfiMaxMemoryType, 0x000 }
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};
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EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMasterBootModePpiGuid,
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NULL
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}
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};
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UINT16 mHostBridgeDevId;
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EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
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BOOLEAN mS3Supported = FALSE;
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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(Cacheable ?
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
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0
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) |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddUntestedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddUntestedMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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MemMapInitialization (
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VOID
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)
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{
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//
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// Create Memory Type Information HOB
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//
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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mDefaultMemoryTypeInformation,
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PcdGet64 (PcdPciIoBase),
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PcdGet64 (PcdPciIoSize)
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);
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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if (!mXen) {
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UINT32 TopOfLowRam;
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UINT64 PciExBarBase;
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UINT32 PciBase;
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UINT32 PciSize;
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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PciExBarBase = 0;
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// The MMCONFIG area is expected to fall between the top of low RAM and
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// the base of the 32-bit PCI host aperture.
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//
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PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT (TopOfLowRam <= PciExBarBase);
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ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
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PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
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} else {
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PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
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}
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//
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// address purpose size
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// ------------ -------- -------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 111 KB
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// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
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// 0xFED20000 gap 896 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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PciSize = 0xFC000000 - PciBase;
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AddIoMemoryBaseSizeHob (PciBase, PciSize);
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PcdSet64 (PcdPciMmio32Base, PciBase);
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PcdSet64 (PcdPciMmio32Size, PciSize);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
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//
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// Note: there should be an
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//
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// AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
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//
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// call below, just like the one above for RCBA. However, Linux insists
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// that the MMCONFIG area be marked in the E820 or UEFI memory map as
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// "reserved memory" -- Linux does not content itself with a simple gap
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// in the memory map wherever the MCFG ACPI table points to.
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//
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// This appears to be a safety measure. The PCI Firmware Specification
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// (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
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// *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
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// [...]". (Emphasis added here.)
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//
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// Normally we add memory resource descriptor HOBs in
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// QemuInitializeRam(), and pre-allocate from those with memory
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// allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
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// is most definitely not RAM; so, as an exception, cover it with
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// uncacheable reserved memory right here.
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//
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AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
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BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
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EfiReservedMemoryType);
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}
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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}
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}
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EFI_STATUS
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GetNamedFwCfgBoolean (
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IN CHAR8 *FwCfgFileName,
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OUT BOOLEAN *Setting
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)
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{
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EFI_STATUS Status;
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FIRMWARE_CONFIG_ITEM FwCfgItem;
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UINTN FwCfgSize;
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UINT8 Value[3];
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Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (FwCfgSize > sizeof Value) {
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return EFI_BAD_BUFFER_SIZE;
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}
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QemuFwCfgSelectItem (FwCfgItem);
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QemuFwCfgReadBytes (FwCfgSize, Value);
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if ((FwCfgSize == 1) ||
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(FwCfgSize == 2 && Value[1] == '\n') ||
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(FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
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switch (Value[0]) {
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case '0':
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case 'n':
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case 'N':
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*Setting = FALSE;
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return EFI_SUCCESS;
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case '1':
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case 'y':
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case 'Y':
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*Setting = TRUE;
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return EFI_SUCCESS;
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default:
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break;
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}
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}
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return EFI_PROTOCOL_ERROR;
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}
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#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
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do { \
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BOOLEAN Setting; \
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\
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if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
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"opt/ovmf/" #TokenName, &Setting))) { \
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PcdSetBool (TokenName, Setting); \
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} \
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} while (0)
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VOID
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NoexecDxeInitialization (
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VOID
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)
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{
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UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
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UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
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}
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VOID
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PciExBarInitialization (
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VOID
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)
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{
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union {
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UINT64 Uint64;
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UINT32 Uint32[2];
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} PciExBarBase;
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//
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// We only support the 256MB size for the MMCONFIG area:
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// 256 buses * 32 devices * 8 functions * 4096 bytes config space.
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//
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// The masks used below enforce the Q35 requirements that the MMCONFIG area
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// be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
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//
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// Note that (b) also ensures that the minimum address width we have
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// determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
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// for DXE's page tables to cover the MMCONFIG area.
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//
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PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
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ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
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//
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// Clear the PCIEXBAREN bit first, before programming the high register.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
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//
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// Program the high register. Then program the low register, setting the
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// MMCONFIG area size and enabling decoding at once.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
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PciWrite32 (
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DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
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PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
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);
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}
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VOID
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MiscInitialization (
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VOID
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)
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{
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UINTN PmCmd;
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UINTN Pmba;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU HOB with guest RAM size dependent address width and 16-bits
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// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
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// S3 resume as well, so we build it unconditionally.)
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//
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BuildCpuHob (mPhysMemAddressWidth, 16);
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//
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// Determine platform type and save Host Bridge DID to PCD
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//
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switch (mHostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
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AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
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AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
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AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, mHostBridgeDevId));
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ASSERT (FALSE);
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return;
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}
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PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
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//
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// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
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// has been configured (e.g., by Xen) and skip the setup here.
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// This matches the logic in AcpiTimerLibConstructor ().
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// The PEI phase should be exited with fully accessibe ACPI PM IO space:
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// 1. set PMBA
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//
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PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
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//
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// 2. set PCICMD/IOSE
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//
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PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
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//
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// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// Set Root Complex Register Block BAR
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//
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PciWrite32 (
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POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
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ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
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);
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//
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// Set PCI Express Register Range Base Address
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//
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PciExBarInitialization ();
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}
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}
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|
|
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VOID
|
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BootModeInitialization (
|
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VOID
|
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)
|
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{
|
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EFI_STATUS Status;
|
|
|
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if (CmosRead8 (0xF) == 0xFE) {
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mBootMode = BOOT_ON_S3_RESUME;
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}
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CmosWrite8 (0xF, 0x00);
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Status = PeiServicesSetBootMode (mBootMode);
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ASSERT_EFI_ERROR (Status);
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Status = PeiServicesInstallPpi (mPpiBootMode);
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ASSERT_EFI_ERROR (Status);
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}
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|
|
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VOID
|
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ReserveEmuVariableNvStore (
|
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)
|
|
{
|
|
EFI_PHYSICAL_ADDRESS VariableStore;
|
|
|
|
//
|
|
// Allocate storage for NV variables early on so it will be
|
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// at a consistent address. Since VM memory is preserved
|
|
// across reboots, this allows the NV variable storage to survive
|
|
// a VM reboot.
|
|
//
|
|
VariableStore =
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(EFI_PHYSICAL_ADDRESS)(UINTN)
|
|
AllocateAlignedRuntimePages (
|
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EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
|
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PcdGet32 (PcdFlashNvStorageFtwSpareSize)
|
|
);
|
|
DEBUG ((EFI_D_INFO,
|
|
"Reserved variable store memory: 0x%lX; size: %dkb\n",
|
|
VariableStore,
|
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(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
|
|
));
|
|
PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
|
|
}
|
|
|
|
|
|
VOID
|
|
DebugDumpCmos (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 Loop;
|
|
|
|
DEBUG ((EFI_D_INFO, "CMOS:\n"));
|
|
|
|
for (Loop = 0; Loop < 0x80; Loop++) {
|
|
if ((Loop % 0x10) == 0) {
|
|
DEBUG ((EFI_D_INFO, "%02x:", Loop));
|
|
}
|
|
DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
|
|
if ((Loop % 0x10) == 0xf) {
|
|
DEBUG ((EFI_D_INFO, "\n"));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
VOID
|
|
S3Verification (
|
|
VOID
|
|
)
|
|
{
|
|
#if defined (MDE_CPU_X64)
|
|
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
|
|
DEBUG ((EFI_D_ERROR,
|
|
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
|
|
DEBUG ((EFI_D_ERROR,
|
|
"%a: Please disable S3 on the QEMU command line (see the README),\n",
|
|
__FUNCTION__));
|
|
DEBUG ((EFI_D_ERROR,
|
|
"%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
|
|
ASSERT (FALSE);
|
|
CpuDeadLoop ();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
|
|
/**
|
|
Perform Platform PEI initialization.
|
|
|
|
@param FileHandle Handle of the file being invoked.
|
|
@param PeiServices Describes the list of possible PEI Services.
|
|
|
|
@return EFI_SUCCESS The PEIM initialized successfully.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
InitializePlatform (
|
|
IN EFI_PEI_FILE_HANDLE FileHandle,
|
|
IN CONST EFI_PEI_SERVICES **PeiServices
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
|
|
|
|
DebugDumpCmos ();
|
|
|
|
XenDetect ();
|
|
|
|
if (QemuFwCfgS3Enabled ()) {
|
|
DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
|
|
mS3Supported = TRUE;
|
|
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
|
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
|
|
S3Verification ();
|
|
BootModeInitialization ();
|
|
AddressWidthInitialization ();
|
|
|
|
PublishPeiMemory ();
|
|
|
|
InitializeRamRegions ();
|
|
|
|
if (mXen) {
|
|
DEBUG ((EFI_D_INFO, "Xen was detected\n"));
|
|
InitializeXen ();
|
|
}
|
|
|
|
//
|
|
// Query Host Bridge DID
|
|
//
|
|
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
|
|
|
|
if (mBootMode != BOOT_ON_S3_RESUME) {
|
|
ReserveEmuVariableNvStore ();
|
|
PeiFvInitialization ();
|
|
MemMapInitialization ();
|
|
NoexecDxeInitialization ();
|
|
}
|
|
|
|
MiscInitialization ();
|
|
|
|
return EFI_SUCCESS;
|
|
}
|