audk/OvmfPkg/ResetVector
Zhiguang Liu dea6002d6e OvmfPkg: Remove applicationProcessorEntryPoint
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494

Current reset vector uses 0xffffffe0 as AP waking vector, and expects
GenFv generates code aligned on a 4k boundary which will jump to this
location. However, some issues are listed below
1. GenFV doesn't generate code as the comment expects, because GenFv
assumes no modifications are required to the VTF-0 'Volume Top File'.
2. Even if removing VFT0 signature and let GenFv to modify, Genfv is
hard-code using another flash address 0xffffffd0.
3. In the same patch series, AP waking vector code is removed from
GenFv, because no such usage anymore. The existing of first two issues
also approve the usage is not available for a long time.

Therefore, remove AP waking vector related code.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien@xen.org>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2023-09-18 02:39:25 +00:00
..
Ia16 OvmfPkg: Remove applicationProcessorEntryPoint 2023-09-18 02:39:25 +00:00
Ia32 OvmfPkg/ResetVector: Fix assembler bit test flag check 2023-07-14 22:52:58 +00:00
X64 OvmfPkg/ResetVector: pre-validate the data pages used in SEC phase 2021-12-09 06:28:10 +00:00
Main.asm OvmfPkg: Make an Ia32/X64 hybrid build work with SEV 2022-05-20 06:29:34 +00:00
ResetVector.inf OvmfPkg/ResetVector: pre-validate the data pages used in SEC phase 2021-12-09 06:28:10 +00:00
ResetVector.nasmb OvmfPkg: Make an Ia32/X64 hybrid build work with SEV 2022-05-20 06:29:34 +00:00