Star Zeng e91797885a IntelSiliconPkg MicrocodeUpdateDxe: Honor FIT table ... It is the second step for https://bugzilla.tianocore.org/show_bug.cgi?id=540. V2: Use error handling instead of ASSERT for FIT table checking result. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>		2018-05-09 16:27:30 +08:00
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Capsule	IntelSiliconPkg MicrocodeUpdateDxe: Honor FIT table	2018-05-09 16:27:30 +08:00
VTd	IntelSiliconPkg/Vtd: Add more debug info.	2018-03-20 08:51:54 +08:00