mirror of https://github.com/acidanthera/audk.git
6932f4bfe5
https://bugzilla.tianocore.org/show_bug.cgi?id=3114 Add logic to flush all UART transmit buffers if there is a config change from Reset(), SetAttributes() or SetControl(). Use a timeout in the flush operation, so the system can continue to boot if the transmit buffers can not be flushed for any reason. This change prevents lost characters on serial debug logs and serial consoles when a config change is made. It also prevents a UART from getting into a bad state or reporting error status due to characters being transmitted at the same time registers are updated with new communications settings. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> |
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| EhciDxe | ||
| EhciPei | ||
| IdeBusPei | ||
| IncompatiblePciDeviceSupportDxe | ||
| NonDiscoverablePciDeviceDxe | ||
| NvmExpressDxe | ||
| NvmExpressPei | ||
| PciBusDxe | ||
| PciHostBridgeDxe | ||
| PciSioSerialDxe | ||
| SataControllerDxe | ||
| SdMmcPciHcDxe | ||
| SdMmcPciHcPei | ||
| UfsPciHcDxe | ||
| UfsPciHcPei | ||
| UhciDxe | ||
| UhciPei | ||
| XhciDxe | ||
| XhciPei | ||