mirror of https://github.com/acidanthera/audk.git
158 lines
3.8 KiB
C
158 lines
3.8 KiB
C
/** @file
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Intel FSP Info Header definition from Intel Firmware Support Package External
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Architecture Specification, April 2014, revision 001.
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Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FSP_INFO_HEADER_H_
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#define _FSP_INFO_HEADER_H_
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#define FSP_HEADER_REVISION_1 1
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#define FSP_HEADER_REVISION_2 2
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#define FSPE_HEADER_REVISION_1 1
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#define FSPP_HEADER_REVISION_1 1
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///
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/// Fixed FSP header offset in the FSP image
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///
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#define FSP_INFO_HEADER_OFF 0x94
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#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
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#pragma pack(1)
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typedef struct {
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///
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/// Byte 0x00: Signature ('FSPH') for the FSP Information Header
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///
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UINT32 Signature;
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///
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/// Byte 0x04: Length of the FSP Information Header
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///
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UINT32 HeaderLength;
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///
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/// Byte 0x08: Reserved
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///
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UINT8 Reserved1[3];
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///
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/// Byte 0x0B: Revision of the FSP Information Header
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///
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UINT8 HeaderRevision;
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///
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/// Byte 0x0C: Revision of the FSP binary
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///
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UINT32 ImageRevision;
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///
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/// Byte 0x10: Signature string that will help match the FSP Binary to a supported
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/// hardware configuration.
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///
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CHAR8 ImageId[8];
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///
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/// Byte 0x18: Size of the entire FSP binary
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///
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UINT32 ImageSize;
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///
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/// Byte 0x18: FSP binary preferred base address
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///
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UINT32 ImageBase;
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///
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/// Byte 0x20: Attribute for the FSP binary
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///
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UINT32 ImageAttribute;
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///
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/// Byte 0x24: Offset of the FSP configuration region
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///
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UINT32 CfgRegionOffset;
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///
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/// Byte 0x24: Size of the FSP configuration region
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///
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UINT32 CfgRegionSize;
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///
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/// Byte 0x2C: Number of API entries this FSP supports
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///
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UINT32 ApiEntryNum;
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///
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/// Byte 0x30: The offset for the API to setup a temporary stack till the memory
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/// is initialized.
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///
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UINT32 TempRamInitEntryOffset;
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///
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/// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
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///
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UINT32 FspInitEntryOffset;
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///
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/// Byte 0x38: The offset for the API to inform the FSP about the different stages
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/// in the boot process
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///
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UINT32 NotifyPhaseEntryOffset;
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///
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/// Below field is added in FSP 1.1
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///
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///
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/// Byte 0x3C: The offset for the API to initialize the memory
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///
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UINT32 FspMemoryInitEntryOffset;
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///
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/// Byte 0x40: The offset for the API to tear down temporary RAM
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///
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UINT32 TempRamExitEntryOffset;
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///
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/// Byte 0x44: The offset for the API to initialize the CPU and chipset
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///
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UINT32 FspSiliconInitEntryOffset;
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} FSP_INFO_HEADER;
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///
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/// Below structure is added in FSP 1.1
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///
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typedef struct {
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///
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/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
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///
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UINT32 Signature;
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///
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/// Byte 0x04: Length of the FSP Extended Header
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///
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UINT32 HeaderLength;
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///
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/// Byte 0x08: Revision of the FSP Extended Header
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///
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UINT8 Revision;
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///
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/// Byte 0x09: Reserved for future use.
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///
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UINT8 Reserved;
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///
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/// Byte 0x0A: An OEM-supplied string that defines the OEM
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///
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CHAR8 OemId[6];
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///
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/// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.
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///
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UINT32 OemRevision;
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} FSP_EXTENTED_HEADER;
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#pragma pack()
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#endif
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