mirror of https://github.com/acidanthera/audk.git
403 lines
14 KiB
C
403 lines
14 KiB
C
/** @file
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Implementation shared across all library instances.
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Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuFeaturesLib.h"
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#include <Library/MtrrLib.h>
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#include <Register/Intel/Cpuid.h>
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#include <Register/Intel/SmramSaveStateMap.h>
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//
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// Machine Specific Registers (MSRs)
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//
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#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
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#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
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#define EFI_MSR_SMRR_MASK 0xFFFFF000
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#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
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#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
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//
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// MSRs required for configuration of SMM Code Access Check
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//
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#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
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#define SMM_CODE_ACCESS_CHK_BIT BIT58
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//
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// Set default value to assume IA-32 Architectural MSRs are used
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//
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UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
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UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
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//
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// Set default value to assume MTRRs need to be configured on each SMI
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//
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BOOLEAN mNeedConfigureMtrrs = TRUE;
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//
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// Array for state of SMRR enable on all CPUs
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//
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BOOLEAN *mSmrrEnabled;
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/**
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Performs library initialization.
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This initialization function contains common functionality shared betwen all
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library instance constructors.
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**/
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VOID
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CpuFeaturesLibInitialization (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN FamilyId;
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UINTN ModelId;
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//
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// Retrieve CPU Family and Model
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//
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AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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}
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//
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// Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
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//
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if ((RegEdx & BIT12) != 0) {
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//
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// Check MTRR_CAP MSR bit 11 for SMRR support
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
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ASSERT (FeaturePcdGet (PcdSmrrEnable));
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
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//
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// If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
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// SMRR Physical Base and SMM Physical Mask MSRs are not available.
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//
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if (FamilyId == 0x06) {
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if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {
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ASSERT (!FeaturePcdGet (PcdSmrrEnable));
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
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//
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// If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
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// Processor Family MSRs
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//
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if (FamilyId == 0x06) {
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if ((ModelId == 0x17) || (ModelId == 0x0f)) {
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mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
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mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 34.4.2 SMRAM Caching
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// An IA-32 processor does not automatically write back and invalidate its
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// caches before entering SMM or before exiting SMM. Because of this behavior,
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// care must be taken in the placement of the SMRAM in system memory and in
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// the caching of the SMRAM to prevent cache incoherence when switching back
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// and forth between SMM and protected mode operation.
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//
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// An IA-32 processor is a processor that does not support the Intel 64
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// Architecture. Support for the Intel 64 Architecture can be detected from
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// CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
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//
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// If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
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// so caches are flushed on SMI entry and SMI exit, the interrupted code
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// MTRRs are saved/restored, and MTRRs for SMM are loaded.
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//
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AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
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if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
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AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT29) != 0) {
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mNeedConfigureMtrrs = FALSE;
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}
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}
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//
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// Allocate array for state of SMRR enable on all CPUs
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//
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mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ());
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ASSERT (mSmrrEnabled != NULL);
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}
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/**
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Called during the very first SMI into System Management Mode to initialize
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CPU features, including SMBASE, for the currently executing CPU. Since this
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is the first SMI, the SMRAM Save State Map is at the default address of
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SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
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CPU is specified by CpuIndex and CpuIndex can be used to access information
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about the currently executing CPU in the ProcessorInfo array and the
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HotPlugCpuData data structure.
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@param[in] CpuIndex The index of the CPU to initialize. The value
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must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
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was elected as monarch during System Management
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Mode initialization.
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FALSE if the CpuIndex is not the index of the CPU
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that was elected as monarch during System
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Management Mode initialization.
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@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
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structures. ProcessorInfo[CpuIndex] contains the
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information for the currently executing CPU.
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@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
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contains the ApidId and SmBase arrays.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesInitializeProcessor (
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IN UINTN CpuIndex,
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IN BOOLEAN IsMonarch,
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IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
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IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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)
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{
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SMRAM_SAVE_STATE_MAP *CpuState;
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UINT64 FeatureControl;
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN FamilyId;
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UINTN ModelId;
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//
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// Configure SMBASE.
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//
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CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
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CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
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//
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// If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
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// make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
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// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
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// is set, then the MSR is locked and can not be modified.
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//
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if ((FeaturePcdGet (PcdSmrrEnable)) && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
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FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
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if ((FeatureControl & BIT3) == 0) {
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ASSERT ((FeatureControl & BIT0) == 0);
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if ((FeatureControl & BIT0) == 0) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
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}
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}
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}
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//
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// If SMRR is supported, then program SMRR base/mask MSRs.
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// The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
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// The code that initializes SMM environment is running in normal mode
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// from SMRAM region. If SMRR is enabled here, then the SMRAM region
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// is protected and the normal mode code execution will fail.
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//
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if (FeaturePcdGet (PcdSmrrEnable)) {
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//
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// SMRR size cannot be less than 4-KBytes
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// SMRR size must be of length 2^n
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// SMRR base alignment cannot be less than SMRR length
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//
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if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
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(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
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((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
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{
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//
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// Print message and halt if CPU is Monarch
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//
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if (IsMonarch) {
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DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
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CpuDeadLoop ();
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}
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} else {
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AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);
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AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));
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mSmrrEnabled[CpuIndex] = FALSE;
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}
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}
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//
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// Retrieve CPU Family and Model
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//
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AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
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// Processor Family.
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//
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// If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
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// Intel(R) Core(TM) Processor Family MSRs.
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//
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if (FamilyId == 0x06) {
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if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||
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(ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||
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(ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||
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(ModelId == 0x8C))
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{
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//
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// Check to see if the CPU supports the SMM Code Access Check feature
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// Do not access this MSR unless the CPU supports the SmmRegFeatureControl
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {
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ASSERT (FeaturePcdGet (PcdSmmFeatureControlEnable));
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}
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}
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}
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//
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// Call internal worker function that completes the CPU initialization
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//
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FinishSmmCpuFeaturesInitializeProcessor ();
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}
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/**
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Determines if MTRR registers must be configured to set SMRAM cache-ability
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when executing in System Management Mode.
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@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
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@retval FALSE MTRR registers do not need to be configured to set SMRAM
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cache-ability.
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**/
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BOOLEAN
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EFIAPI
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SmmCpuFeaturesNeedConfigureMtrrs (
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VOID
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)
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{
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return mNeedConfigureMtrrs;
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}
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/**
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Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesDisableSmrr (
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VOID
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)
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{
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if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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}
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/**
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Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesReenableSmrr (
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VOID
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)
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{
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if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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}
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/**
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Processor specific hook point each time a CPU enters System Management Mode.
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@param[in] CpuIndex The index of the CPU that has entered SMM. The value
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must be between 0 and the NumberOfCpus field in the
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System Management System Table (SMST).
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesRendezvousEntry (
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IN UINTN CpuIndex
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)
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{
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//
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// If SMRR is supported and this is the first normal SMI, then enable SMRR
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//
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if (FeaturePcdGet (PcdSmrrEnable) && !mSmrrEnabled[CpuIndex]) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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mSmrrEnabled[CpuIndex] = TRUE;
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}
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}
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/**
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Returns the current value of the SMM register for the specified CPU.
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If the SMM register is not supported, then 0 is returned.
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@param[in] CpuIndex The index of the CPU to read the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to read.
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@return The value of the SMM register specified by RegName from the CPU
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specified by CpuIndex.
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**/
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UINT64
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EFIAPI
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SmmCpuFeaturesGetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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)
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{
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if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
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return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
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}
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return 0;
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}
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/**
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Sets the value of an SMM register on a specified CPU.
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If the SMM register is not supported, then no action is performed.
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@param[in] CpuIndex The index of the CPU to write the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to write.
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registers are read-only.
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@param[in] Value The value to write to the SMM register.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesSetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName,
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IN UINT64 Value
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)
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{
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if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
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}
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}
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