mirror of https://github.com/acidanthera/audk.git
211 lines
6.4 KiB
C
211 lines
6.4 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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PchCommonDefinitions.h
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Abstract:
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This header file provides common definitions for PCH
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--*/
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#ifndef _PCH_COMMON_DEFINITIONS_H_
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#define _PCH_COMMON_DEFINITIONS_H_
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//
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// MMIO access macros
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//
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#define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))
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//
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// 32 bit MMIO access
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//
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#define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))
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#define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)
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#define PchMmio32Or(BaseAddr, Register, OrData) \
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PchMmio32 (BaseAddr, Register) = (UINT32) \
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(PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
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#define PchMmio32And(BaseAddr, Register, AndData) \
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PchMmio32 (BaseAddr, Register) = (UINT32) \
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(PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))
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#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
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PchMmio32 (BaseAddr, Register) = (UINT32) \
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((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
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//
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// 16 bit MMIO access
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//
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#define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))
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#define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register)
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#define PchMmio16Or(BaseAddr, Register, OrData) \
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PchMmio16 (BaseAddr, Register) = (UINT16) \
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(PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))
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#define PchMmio16And(BaseAddr, Register, AndData) \
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PchMmio16 (BaseAddr, Register) = (UINT16) \
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(PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))
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#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
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PchMmio16 (BaseAddr, Register) = (UINT16) \
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((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
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//
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// 8 bit MMIO access
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//
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#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))
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#define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register)
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#define PchMmio8Or(BaseAddr, Register, OrData) \
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PchMmio8 (BaseAddr, Register) = (UINT8) \
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(PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))
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#define PchMmio8And(BaseAddr, Register, AndData) \
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PchMmio8 (BaseAddr, Register) = (UINT8) \
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(PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))
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#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \
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PchMmio8 (BaseAddr, Register) = (UINT8) \
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((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
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//
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// Memory Mapped PCI Access macros
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//
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#define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000
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//
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// PCI Device MM Base
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//
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#define PchPciDeviceMmBase(Bus, Device, Function) \
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( \
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(UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
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(Function << 12) \
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)
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//
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// PCI Device MM Address
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//
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#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \
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( \
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(UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
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(Function << 12) + (UINTN) (Register) \
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)
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//
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// 32 bit PCI access
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//
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#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \
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((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
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#define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)
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#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \
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PchMmPci32 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))
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#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \
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PchMmPci32 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))
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#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
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PchMmPci32 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
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//
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// 16 bit PCI access
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//
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#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \
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((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
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#define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)
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#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \
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PchMmPci16 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))
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#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \
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PchMmPci16 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))
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#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
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PchMmPci16 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
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//
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// 8 bit PCI access
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//
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#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \
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((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
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#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)
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#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \
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PchMmPci8 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))
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#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \
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PchMmPci8 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))
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#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
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PchMmPci8 ( \
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Segment, \
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Bus, \
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Device, \
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Function, \
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Register \
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) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
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#endif
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