mirror of https://github.com/acidanthera/audk.git
84 lines
4.4 KiB
C
84 lines
4.4 KiB
C
/**
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@file
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PchRegsPcie.h
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@brief
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Register names for VLV PCI-E root port devices
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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--*/
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#ifndef _PCH_REGS_PCIE_H_
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#define _PCH_REGS_PCIE_H_
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#define PCH_PCIE_MAX_ROOT_PORTS 4
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///
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/// VLV PCI Express Root Ports (D28:F0~F3)
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///
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
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#define R_PCH_PCIE_ID 0x00 // Identifiers
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#define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID
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#define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1
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#define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2
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#define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3
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#define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4
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#define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID
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#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer
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#define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer
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#define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number
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#define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number
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#define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number
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#define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer
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#define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer
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#define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status
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#define S_PCH_PCIE_SLCTL_SLSTS 4
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#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed
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#define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
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#define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
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#define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
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#define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
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#define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected
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#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable
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#define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control
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#define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable
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#define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
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#define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable
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#define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs
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#define S_PCH_PCIE_SVID 4
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#define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier
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#define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier
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#endif
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