mirror of https://github.com/acidanthera/audk.git
256 lines
8.6 KiB
C
256 lines
8.6 KiB
C
/** @file
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Provides services to access SMRAM Save State Map
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Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiSmm.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include "PiSmmCpuDxeSmm.h"
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typedef struct {
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UINT64 Signature; // Offset 0x00
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UINT16 Reserved1; // Offset 0x08
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UINT16 Reserved2; // Offset 0x0A
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UINT16 Reserved3; // Offset 0x0C
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UINT16 SmmCs; // Offset 0x0E
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UINT16 SmmDs; // Offset 0x10
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UINT16 SmmSs; // Offset 0x12
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UINT16 SmmOtherSegment; // Offset 0x14
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UINT16 Reserved4; // Offset 0x16
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UINT64 Reserved5; // Offset 0x18
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UINT64 Reserved6; // Offset 0x20
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UINT64 Reserved7; // Offset 0x28
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UINT64 SmmGdtPtr; // Offset 0x30
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UINT32 SmmGdtSize; // Offset 0x38
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UINT32 Reserved8; // Offset 0x3C
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UINT64 Reserved9; // Offset 0x40
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UINT64 Reserved10; // Offset 0x48
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UINT16 Reserved11; // Offset 0x50
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UINT16 Reserved12; // Offset 0x52
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UINT32 Reserved13; // Offset 0x54
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UINT64 Reserved14; // Offset 0x58
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} PROCESSOR_SMM_DESCRIPTOR;
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extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
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//
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// EFER register LMA bit
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//
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#define LMA BIT10
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///
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/// Variables from SMI Handler
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///
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X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
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extern volatile UINT8 gcSmiHandlerTemplate[];
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extern CONST UINT16 gcSmiHandlerSize;
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//
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// Variables used by SMI Handler
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//
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IA32_DESCRIPTOR gSmiHandlerIdtr;
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///
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/// The mode of the CPU at the time an SMI occurs
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///
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UINT8 mSmmSaveStateRegisterLma;
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/**
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Hook the code executed immediately after an RSM instruction on the currently
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executing CPU. The mode of code executed immediately after RSM must be
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detected, and the appropriate hook must be selected. Always clear the auto
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HALT restart flag if it is set.
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@param[in] CpuIndex The processor index for the currently
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executing CPU.
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@param[in] CpuState Pointer to SMRAM Save State Map for the
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currently executing CPU.
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@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
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32-bit mode from 64-bit SMM.
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@param[in] NewInstructionPointer Instruction pointer to use if resuming to
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same mode as SMM.
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@retval The value of the original instruction pointer before it was hooked.
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**/
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UINT64
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EFIAPI
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HookReturnFromSmm (
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IN UINTN CpuIndex,
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SMRAM_SAVE_STATE_MAP *CpuState,
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UINT64 NewInstructionPointer32,
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UINT64 NewInstructionPointer
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)
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{
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UINT64 OriginalInstructionPointer;
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OriginalInstructionPointer = SmmCpuFeaturesHookReturnFromSmm (
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CpuIndex,
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CpuState,
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NewInstructionPointer32,
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NewInstructionPointer
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);
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if (OriginalInstructionPointer != 0) {
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return OriginalInstructionPointer;
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}
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if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
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OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;
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CpuState->x86._EIP = (UINT32)NewInstructionPointer;
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) {
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CpuState->x86.AutoHALTRestart &= ~BIT0;
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}
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} else {
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OriginalInstructionPointer = CpuState->x64._RIP;
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if ((CpuState->x64.IA32_EFER & LMA) == 0) {
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CpuState->x64._RIP = (UINT32)NewInstructionPointer32;
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} else {
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CpuState->x64._RIP = (UINT32)NewInstructionPointer;
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}
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) {
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CpuState->x64.AutoHALTRestart &= ~BIT0;
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}
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}
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return OriginalInstructionPointer;
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}
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/**
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Get the size of the SMI Handler in bytes.
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@retval The size, in bytes, of the SMI Handler.
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**/
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UINTN
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EFIAPI
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GetSmiHandlerSize (
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VOID
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)
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{
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UINTN Size;
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Size = SmmCpuFeaturesGetSmiHandlerSize ();
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if (Size != 0) {
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return Size;
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}
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return gcSmiHandlerSize;
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}
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/**
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Install the SMI handler for the CPU specified by CpuIndex. This function
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is called by the CPU that was elected as monarch during System Management
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Mode initialization.
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@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
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The value must be between 0 and the NumberOfCpus field
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in the System Management System Table (SMST).
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@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
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@param[in] SmiStack The stack to use when an SMI is processed by the
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the CPU specified by CpuIndex.
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@param[in] StackSize The size, in bytes, if the stack used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtBase The base address of the GDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtBase The base address of the IDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] Cr3 The base address of the page tables to use when an SMI
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is processed by the CPU specified by CpuIndex.
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**/
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VOID
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EFIAPI
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InstallSmiHandler (
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IN UINTN CpuIndex,
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IN UINT32 SmBase,
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IN VOID *SmiStack,
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IN UINTN StackSize,
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IN UINTN GdtBase,
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IN UINTN GdtSize,
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IN UINTN IdtBase,
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IN UINTN IdtSize,
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IN UINT32 Cr3
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)
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{
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PROCESSOR_SMM_DESCRIPTOR *Psd;
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UINT32 CpuSmiStack;
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//
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// Initialize PROCESSOR_SMM_DESCRIPTOR
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//
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Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);
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CopyMem (Psd, &gcPsd, sizeof (gcPsd));
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Psd->SmmGdtPtr = (UINT64)GdtBase;
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Psd->SmmGdtSize = (UINT32)GdtSize;
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if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
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//
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// Install SMI handler provided by library
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//
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SmmCpuFeaturesInstallSmiHandler (
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CpuIndex,
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SmBase,
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SmiStack,
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StackSize,
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GdtBase,
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GdtSize,
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IdtBase,
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IdtSize,
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Cr3
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);
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return;
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}
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InitShadowStack (CpuIndex, (VOID *)((UINTN)SmiStack + StackSize));
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//
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// Initialize values in template before copy
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//
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CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
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PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);
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PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);
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PatchInstructionX86 (gPatchSmbase, SmBase, 4);
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gSmiHandlerIdtr.Base = IdtBase;
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gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
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//
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// Set the value at the top of the CPU stack to the CPU Index
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//
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*(UINTN *)(UINTN)CpuSmiStack = CpuIndex;
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//
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// Copy template to CPU specific SMI handler location
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//
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CopyMem (
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(VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
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(VOID *)gcSmiHandlerTemplate,
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gcSmiHandlerSize
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);
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}
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