mirror of https://github.com/acidanthera/audk.git
778 lines
24 KiB
C
778 lines
24 KiB
C
/** @file
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Lib function for Pei QNC.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CommonHeader.h"
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/**
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This function provides the necessary SOC initialization
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before MRC running. It sets RCBA, GPIO, PMBASE
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and some parts of SOC through SOC message method.
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If the function cannot complete it'll ASSERT().
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**/
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VOID
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EFIAPI
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PeiQNCPreMemInit (
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VOID
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)
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{
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UINT32 RegValue;
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// QNCPortWrite(Port#, Offset, Value)
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//
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// Set the fixed PRI Status encodings config.
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//
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QNCPortWrite (
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QUARK_NC_MEMORY_ARBITER_SB_PORT_ID,
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QUARK_NC_MEMORY_ARBITER_REG_ASTATUS,
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QNC_FIXED_CONFIG_ASTATUS
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);
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// Sideband register write to Remote Management Unit
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QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QNC_MSG_TMPM_REG_PMBA, (BIT31 | PcdGet16 (PcdPmbaIoBaseAddress)));
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// Configurable I/O address in iLB (legacy block)
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LpcPciCfg32 (R_QNC_LPC_SMBUS_BASE) = BIT31 | PcdGet16 (PcdSmbaIoBaseAddress);
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LpcPciCfg32 (R_QNC_LPC_GBA_BASE) = BIT31 | PcdGet16 (PcdGbaIoBaseAddress);
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LpcPciCfg32 (R_QNC_LPC_PM1BLK) = BIT31 | PcdGet16 (PcdPm1blkIoBaseAddress);
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LpcPciCfg32 (R_QNC_LPC_GPE0BLK) = BIT31 | PcdGet16 (PcdGpe0blkIoBaseAddress);
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LpcPciCfg32 (R_QNC_LPC_WDTBA) = BIT31 | PcdGet16 (PcdWdtbaIoBaseAddress);
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//
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// Program RCBA Base Address
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//
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LpcPciCfg32AndThenOr (R_QNC_LPC_RCBA, (~B_QNC_LPC_RCBA_MASK), (((UINT32)(PcdGet64 (PcdRcbaMmioBaseAddress))) | B_QNC_LPC_RCBA_EN));
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//
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// Program Memory Manager fixed config values.
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//
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RegValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BTHCTRL);
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RegValue &= ~(DRAM_NON_HOST_RQ_LIMIT_MASK);
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RegValue |= (V_DRAM_NON_HOST_RQ_LIMIT << DRAM_NON_HOST_RQ_LIMIT_BP);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BTHCTRL, RegValue);
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//
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// Program iCLK fixed config values.
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//
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QncIClkAndThenOr (
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QUARK_ICLK_MUXTOP,
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(UINT32) ~(B_MUXTOP_FLEX2_MASK | B_MUXTOP_FLEX1_MASK),
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(V_MUXTOP_FLEX2 << B_MUXTOP_FLEX2_BP) | (V_MUXTOP_FLEX1 << B_MUXTOP_FLEX1_BP)
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);
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QncIClkAndThenOr (
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QUARK_ICLK_REF2_DBUFF0,
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(UINT32) ~(BIT0), // bit[0] cleared
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0
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);
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QncIClkOr (
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QUARK_ICLK_SSC1,
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BIT0 // bit[0] set
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);
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QncIClkOr (
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QUARK_ICLK_SSC2,
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BIT0 // bit[0] set
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);
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QncIClkOr (
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QUARK_ICLK_SSC3,
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BIT0 // bit[0] set
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);
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//
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// Set RMU DMA disable bit post boot.
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//
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RegValue = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_OPTIONS_1);
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RegValue |= OPTIONS_1_DMA_DISABLE;
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QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_OPTIONS_1, RegValue);
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}
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/**
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Do north cluster init which needs to be done AFTER MRC init.
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@param VOID
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@retval VOID
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**/
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VOID
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EFIAPI
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PeiQNCPostMemInit (
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VOID
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)
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{
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//
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// Program SVID/SID the same as VID/DID for all devices except root ports.
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//
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QNCMmPci32(0, MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID) = QNCMmPci32(0, MC_BUS, MC_DEV, MC_FUN, PCI_VENDOR_ID_OFFSET);
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QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, PCI_VENDOR_ID_OFFSET);
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QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, PCI_VENDOR_ID_OFFSET);
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QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, R_EFI_PCI_SVID) = QNCMmPci32(0, PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1, PCI_FUNCTION_NUMBER_QNC_IOSF2AHB, PCI_VENDOR_ID_OFFSET);
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return;
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}
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/**
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Used to check QNC if it's S3 state. Clear the register state after query.
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@retval TRUE if it's S3 state.
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@retval FALSE if it's not S3 state.
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**/
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BOOLEAN
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EFIAPI
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QNCCheckS3AndClearState (
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VOID
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)
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{
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BOOLEAN S3WakeEventFound;
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UINT16 Pm1Sts;
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UINT16 Pm1En;
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UINT16 Pm1Cnt;
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UINT32 Gpe0Sts;
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UINT32 Gpe0En;
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UINT32 NewValue;
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CHAR8 *EventDescStr;
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S3WakeEventFound = FALSE;
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EventDescStr = NULL;
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//
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// Read the ACPI registers,
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//
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Pm1Sts = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S);
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Pm1En = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E);
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Pm1Cnt = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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Gpe0Sts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S);
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Gpe0En = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0E);
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//
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// Clear Power Management 1 Enable Register and
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// General Purpost Event 0 Enables Register
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//
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IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E, 0);
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IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0E, 0);
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if ((Pm1Sts & B_QNC_PM1BLK_PM1S_WAKE) != 0 && (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) == V_S3) {
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//
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// Detect the actual WAKE event
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//
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if ((Pm1Sts & B_QNC_PM1BLK_PM1S_RTC) && (Pm1En & B_QNC_PM1BLK_PM1E_RTC)) {
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EventDescStr = "RTC Alarm";
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S3WakeEventFound = TRUE;
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}
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if ((Pm1Sts & B_QNC_PM1BLK_PM1S_PCIEWSTS) && !(Pm1En & B_QNC_PM1BLK_PM1E_PWAKED)) {
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EventDescStr = "PCIe WAKE";
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S3WakeEventFound = TRUE;
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}
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if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_PCIE) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_PCIE)) {
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EventDescStr = "PCIe";
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S3WakeEventFound = TRUE;
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}
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if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_GPIO) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_GPIO)) {
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EventDescStr = "GPIO";
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S3WakeEventFound = TRUE;
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}
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if ((Gpe0Sts & B_QNC_GPE0BLK_GPE0S_EGPE) && (Gpe0En & B_QNC_GPE0BLK_GPE0E_EGPE)) {
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EventDescStr = "Ext. GPE";
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S3WakeEventFound = TRUE;
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}
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if (S3WakeEventFound == FALSE) {
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EventDescStr = "Unknown";
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}
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DEBUG ((EFI_D_INFO, "S3 Wake Event - %a\n", EventDescStr));
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//
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// If no Power Button Override event occurs and one enabled wake event occurs,
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// just do S3 resume and clear the state.
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//
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IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, (Pm1Cnt & (~B_QNC_PM1BLK_PM1C_SLPTP)));
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//
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// Set EOS to de Assert SMI
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//
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IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_EOS);
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//
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// Enable SMI globally
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//
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NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
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NewValue |= SMI_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);
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return TRUE;
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}
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return FALSE;
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}
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/**
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Used to check QNC if system wakes up from power on reset. Clear the register state after query.
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@retval TRUE if system wakes up from power on reset
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@retval FALSE if system does not wake up from power on reset
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**/
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BOOLEAN
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EFIAPI
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QNCCheckPowerOnResetAndClearState (
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VOID
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)
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{
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UINT16 Pm1Sts;
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UINT16 Pm1Cnt;
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//
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// Read the ACPI registers,
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// PM1_STS information cannot be lost after power down, unless CMOS is cleared.
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//
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Pm1Sts = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S);
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Pm1Cnt = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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//
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// If B_SLP_TYP is S5
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//
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if ((Pm1Sts & B_QNC_PM1BLK_PM1S_WAKE) != 0 && (Pm1Cnt & B_QNC_PM1BLK_PM1C_SLPTP) == V_S5) {
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IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, (Pm1Cnt & (~B_QNC_PM1BLK_PM1C_SLPTP)));
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return TRUE;
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}
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return FALSE;
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}
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/**
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This function is used to clear SMI and wake status.
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**/
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VOID
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EFIAPI
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QNCClearSmiAndWake (
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VOID
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)
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{
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UINT32 Gpe0Sts;
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UINT32 SmiSts;
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//
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// Read the ACPI registers
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//
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Gpe0Sts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S);
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SmiSts = IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS);
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//
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// Clear any SMI or wake state from the boot
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//
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Gpe0Sts |= B_QNC_GPE0BLK_GPE0S_ALL;
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SmiSts |= B_QNC_GPE0BLK_SMIS_ALL;
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//
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// Write them back
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//
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IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S, Gpe0Sts);
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IoWrite32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS, SmiSts);
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}
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/** Send DRAM Ready opcode.
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@param[in] OpcodeParam Parameter to DRAM ready opcode.
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@retval VOID
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**/
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VOID
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EFIAPI
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QNCSendOpcodeDramReady (
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IN UINT32 OpcodeParam
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)
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{
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//
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// Before sending DRAM ready place invalid value in Scrub Config.
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//
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QNCPortWrite (
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QUARK_NC_RMU_SB_PORT_ID,
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QUARK_NC_ECC_SCRUB_CONFIG_REG,
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SCRUB_CFG_INVALID
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);
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//
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// Send opcode and use param to notify HW of new RMU firmware location.
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//
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McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = OpcodeParam;
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_SHADOW_DW (QUARK_NC_RMU_SB_PORT_ID, 0);
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//
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// HW completed tasks on DRAM ready when scrub config read back as zero.
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//
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while (QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG) != 0) {
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MicroSecondDelay (10);
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}
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}
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/**
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Relocate RMU Main binary to memory after MRC to improve performance.
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@param[in] DestBaseAddress - Specify the new memory address for the RMU Main binary.
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@param[in] SrcBaseAddress - Specify the current memory address for the RMU Main binary.
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@param[in] Size - Specify size of the RMU Main binary.
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@retval VOID
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**/
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VOID
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EFIAPI
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RmuMainRelocation (
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IN CONST UINT32 DestBaseAddress,
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IN CONST UINT32 SrcBaseAddress,
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IN CONST UINTN Size
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)
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{
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//
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// Shadow RMU Main binary into main memory.
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//
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CopyMem ((VOID *)(UINTN)DestBaseAddress,(VOID *)(UINTN) SrcBaseAddress, Size);
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}
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/**
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Get the total memory size
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**/
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UINT32
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EFIAPI
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QNCGetTotalMemorysize (
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VOID
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)
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{
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return QNCPortRead(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG) & HMBOUND_MASK;
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}
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/**
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Get the memory range of TSEG.
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The TSEG's memory is below TOLM.
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@param[out] BaseAddress The base address of TSEG's memory range
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@param[out] MemorySize The size of TSEG's memory range
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**/
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VOID
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EFIAPI
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QNCGetTSEGMemoryRange (
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OUT UINT64 *BaseAddress,
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OUT UINT64 *MemorySize
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)
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{
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UINT64 Register = 0;
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UINT64 SMMAddress = 0;
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Register = QncHsmmcRead ();
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//
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// Get the SMRAM Base address
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//
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SMMAddress = Register & SMM_START_MASK;
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*BaseAddress = LShift16 (SMMAddress);
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//
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// Get the SMRAM size
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//
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SMMAddress = ((Register & SMM_END_MASK) | (~SMM_END_MASK)) + 1;
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*MemorySize = SMMAddress - (*BaseAddress);
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DEBUG ((
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EFI_D_INFO,
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"TSEG's memory range: BaseAddress = 0x%x, Size = 0x%x\n",
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(UINT32)*BaseAddress,
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(UINT32)*MemorySize
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));
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}
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/**
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Updates the PAM registers in the MCH for the requested range and mode.
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@param Start The start address of the memory region
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@param Length The length, in bytes, of the memory region
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@param ReadEnable Pointer to the boolean variable on whether to enable read for legacy memory section.
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If NULL, then read attribute will not be touched by this call.
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@param ReadEnable Pointer to the boolean variable on whether to enable write for legacy memory section.
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If NULL, then write attribute will not be touched by this call.
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@param Granularity A pointer to granularity, in bytes, that the PAM registers support
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@retval RETURN_SUCCESS The PAM registers in the MCH were updated
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@retval RETURN_INVALID_PARAMETER The memory range is not valid in legacy region.
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**/
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EFI_STATUS
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EFIAPI
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QNCLegacyRegionManipulation (
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IN UINT32 Start,
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IN UINT32 Length,
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IN BOOLEAN *ReadEnable,
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IN BOOLEAN *WriteEnable,
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OUT UINT32 *Granularity
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)
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{
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//
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// Do nothing cos no such support on QNC
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//
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return RETURN_SUCCESS;
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}
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/**
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Determine if QNC is supported.
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@retval FALSE QNC is not supported.
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@retval TRUE QNC is supported.
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**/
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BOOLEAN
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EFIAPI
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IsQncSupported (
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VOID
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)
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{
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UINT16 SocVendorId;
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UINT16 SocDeviceId;
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SocVendorId = MmioRead16 (
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PciDeviceMmBase (MC_BUS,
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MC_DEV,
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MC_FUN) + PCI_VENDOR_ID_OFFSET
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);
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SocDeviceId = QncGetSocDeviceId();
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//
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// Verify that this is a supported chipset
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//
|
|
if ((SocVendorId != QUARK_MC_VENDOR_ID) || ((SocDeviceId != QUARK_MC_DEVICE_ID) && (SocDeviceId != QUARK2_MC_DEVICE_ID))) {
|
|
DEBUG ((DEBUG_ERROR, "QNC code doesn't support the Soc VendorId:0x%04x Soc DeviceId:0x%04x!\n", SocVendorId, SocDeviceId));
|
|
return FALSE;
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
/**
|
|
Get the DeviceId of the SoC
|
|
|
|
@retval PCI DeviceId of the SoC
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
QncGetSocDeviceId (
|
|
VOID
|
|
)
|
|
{
|
|
UINT16 SocDeviceId;
|
|
|
|
SocDeviceId = MmioRead16 (
|
|
PciDeviceMmBase (
|
|
MC_BUS,
|
|
MC_DEV,
|
|
MC_FUN
|
|
) + PCI_DEVICE_ID_OFFSET
|
|
);
|
|
|
|
return SocDeviceId;
|
|
}
|
|
|
|
/**
|
|
Enable SMI detection of legacy flash access violations.
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
QncEnableLegacyFlashAccessViolationSmi (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 BcValue;
|
|
|
|
BcValue = LpcPciCfg32 (R_QNC_LPC_BIOS_CNTL);
|
|
|
|
//
|
|
// Clear BIOSWE & set BLE.
|
|
//
|
|
BcValue &= (~B_QNC_LPC_BIOS_CNTL_BIOSWE);
|
|
BcValue |= (B_QNC_LPC_BIOS_CNTL_BLE);
|
|
|
|
LpcPciCfg32 (R_QNC_LPC_BIOS_CNTL) = BcValue;
|
|
|
|
DEBUG ((EFI_D_INFO, "BIOS Control Lock Enabled!\n"));
|
|
}
|
|
|
|
/**
|
|
Setup RMU Thermal sensor registers for Vref mode.
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
QNCThermalSensorSetVRefMode (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 Tscgf1Config;
|
|
UINT32 Tscgf2Config;
|
|
UINT32 Tscgf2Config2;
|
|
|
|
Tscgf1Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG);
|
|
Tscgf2Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG);
|
|
Tscgf2Config2 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGEN);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_IBGEN_VREF_MODE << B_TSCGF1_CONFIG_IBGEN_BP);
|
|
|
|
Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ISPARECTRL_MASK);
|
|
Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE << B_TSCGF2_CONFIG2_ISPARECTRL_BP);
|
|
|
|
Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK);
|
|
Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP);
|
|
|
|
Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK);
|
|
Tscgf2Config |= (V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE << B_TSCGF2_CONFIG_IDSCONTROL_BP);
|
|
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, Tscgf1Config);
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, Tscgf2Config);
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, Tscgf2Config2);
|
|
}
|
|
|
|
/**
|
|
Setup RMU Thermal sensor registers for Ratiometric mode.
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
QNCThermalSensorSetRatiometricMode (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 Tscgf1Config;
|
|
UINT32 Tscgf2Config;
|
|
UINT32 Tscgf2Config2;
|
|
UINT32 Tscgf3Config;
|
|
|
|
Tscgf1Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG);
|
|
Tscgf2Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG);
|
|
Tscgf2Config2 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2);
|
|
Tscgf3Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_ISNSINTERNALVREFEN);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGEN);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE << B_TSCGF1_CONFIG_IBGEN_BP);
|
|
|
|
Tscgf1Config &= ~(B_TSCGF1_CONFIG_IBGCHOPEN);
|
|
Tscgf1Config |= (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE << B_TSCGF1_CONFIG_IBGCHOPEN_BP);
|
|
|
|
Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK);
|
|
Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP);
|
|
|
|
Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ISPARECTRL_MASK);
|
|
Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE << B_TSCGF2_CONFIG2_ISPARECTRL_BP);
|
|
|
|
Tscgf2Config2 &= ~(B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK);
|
|
Tscgf2Config2 |= (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP);
|
|
|
|
Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK);
|
|
Tscgf2Config |= (V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE << B_TSCGF2_CONFIG_IDSCONTROL_BP);
|
|
|
|
Tscgf2Config &= ~(B_TSCGF2_CONFIG_IDSTIMING_MASK);
|
|
Tscgf2Config |= (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE << B_TSCGF2_CONFIG_IDSTIMING_BP);
|
|
|
|
Tscgf3Config &= ~(B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK);
|
|
Tscgf3Config |= (V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP);
|
|
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, Tscgf1Config);
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, Tscgf2Config);
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, Tscgf2Config2);
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, Tscgf3Config);
|
|
}
|
|
|
|
/**
|
|
Setup RMU Thermal sensor trip point values.
|
|
|
|
@param[in] CatastrophicTripOnDegreesCelsius - Catastrophic set trip point threshold.
|
|
@param[in] HotTripOnDegreesCelsius - Hot set trip point threshold.
|
|
@param[in] HotTripOffDegreesCelsius - Hot clear trip point threshold.
|
|
|
|
@retval EFI_SUCCESS Trip points setup.
|
|
@retval EFI_INVALID_PARAMETER Invalid trip point value.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
QNCThermalSensorSetTripValues (
|
|
IN CONST UINTN CatastrophicTripOnDegreesCelsius,
|
|
IN CONST UINTN HotTripOnDegreesCelsius,
|
|
IN CONST UINTN HotTripOffDegreesCelsius
|
|
)
|
|
{
|
|
UINT32 RegisterValue;
|
|
|
|
//
|
|
// Register fields are 8-bit temperature values of granularity 1 degree C
|
|
// where 0x00 corresponds to -50 degrees C
|
|
// and 0xFF corresponds to 205 degrees C.
|
|
//
|
|
// User passes unsigned values in degrees Celsius so trips < 0 not supported.
|
|
//
|
|
// Add 50 to user values to get values for register fields.
|
|
//
|
|
|
|
if ((CatastrophicTripOnDegreesCelsius > 205) || (HotTripOnDegreesCelsius > 205) || (HotTripOffDegreesCelsius > 205)) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Set new values.
|
|
//
|
|
RegisterValue =
|
|
((0 + 50) << TS_CAT_TRIP_CLEAR_THOLD_BP) | // Cat Trip Clear value must be less than Cat Trip Set Value.
|
|
((CatastrophicTripOnDegreesCelsius + 50) << TS_CAT_TRIP_SET_THOLD_BP) |
|
|
((HotTripOnDegreesCelsius + 50) << TS_HOT_TRIP_SET_THOLD_BP) |
|
|
((HotTripOffDegreesCelsius + 50) << TS_HOT_TRIP_CLEAR_THOLD_BP)
|
|
;
|
|
|
|
QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP, RegisterValue);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Enable RMU Thermal sensor with a Catastrophic Trip point.
|
|
|
|
@retval EFI_SUCCESS Trip points setup.
|
|
@retval EFI_INVALID_PARAMETER Invalid trip point value.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
QNCThermalSensorEnableWithCatastrophicTrip (
|
|
IN CONST UINTN CatastrophicTripOnDegreesCelsius
|
|
)
|
|
{
|
|
UINT32 Tscgf3Config;
|
|
UINT32 TsModeReg;
|
|
UINT32 TsTripReg;
|
|
|
|
//
|
|
// Trip Register fields are 8-bit temperature values of granularity 1 degree C
|
|
// where 0x00 corresponds to -50 degrees C
|
|
// and 0xFF corresponds to 205 degrees C.
|
|
//
|
|
// User passes unsigned values in degrees Celsius so trips < 0 not supported.
|
|
//
|
|
// Add 50 to user values to get values for register fields.
|
|
//
|
|
|
|
if (CatastrophicTripOnDegreesCelsius > 205) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
Tscgf3Config = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG);
|
|
TsModeReg = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_MODE);
|
|
TsTripReg = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP);
|
|
|
|
//
|
|
// Setup Catastrophic Trip point.
|
|
//
|
|
TsTripReg &= ~(TS_CAT_TRIP_SET_THOLD_MASK);
|
|
TsTripReg |= ((CatastrophicTripOnDegreesCelsius + 50) << TS_CAT_TRIP_SET_THOLD_BP);
|
|
TsTripReg &= ~(TS_CAT_TRIP_CLEAR_THOLD_MASK);
|
|
TsTripReg |= ((0 + 50) << TS_CAT_TRIP_CLEAR_THOLD_BP); // Cat Trip Clear value must be less than Cat Trip Set Value.
|
|
QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_TRIP, TsTripReg);
|
|
|
|
//
|
|
// To enable the TS do the following:
|
|
// 1) Take the TS out of reset by setting itsrst to 0x0.
|
|
// 2) Enable the TS using RMU Thermal sensor mode register.
|
|
//
|
|
|
|
Tscgf3Config &= ~(B_TSCGF3_CONFIG_ITSRST);
|
|
TsModeReg |= TS_ENABLE;
|
|
|
|
QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, Tscgf3Config);
|
|
QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_TS_MODE, TsModeReg);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Lock all RMU Thermal sensor control & trip point registers.
|
|
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
QNCThermalSensorLockAllRegisters (
|
|
VOID
|
|
)
|
|
{
|
|
UINT32 RegValue;
|
|
UINT32 LockMask;
|
|
|
|
LockMask = TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE;
|
|
|
|
RegValue = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG);
|
|
RegValue |= LockMask;
|
|
QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG, RegValue);
|
|
|
|
ASSERT ((LockMask == (QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_CONFIG) & LockMask)));
|
|
}
|
|
|
|
/**
|
|
Set chipset policy for double bit ECC error.
|
|
|
|
@param[in] PolicyValue Policy to config on double bit ECC error.
|
|
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
QNCPolicyDblEccBitErr (
|
|
IN CONST UINT32 PolicyValue
|
|
)
|
|
{
|
|
UINT32 Register;
|
|
Register = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_WDT_CONTROL);
|
|
Register &= ~(B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK);
|
|
Register |= PolicyValue;
|
|
QNCPortWrite (
|
|
QUARK_NC_RMU_SB_PORT_ID,
|
|
QUARK_NC_RMU_REG_WDT_CONTROL,
|
|
Register
|
|
);
|
|
}
|
|
|
|
/**
|
|
Determine if running on secure Quark hardware Sku.
|
|
|
|
@retval FALSE Base Quark Sku or unprovisioned Secure Sku running.
|
|
@retval TRUE Provisioned SecureSku hardware running.
|
|
**/
|
|
BOOLEAN
|
|
EFIAPI
|
|
QncIsSecureProvisionedSku (
|
|
VOID
|
|
)
|
|
{
|
|
// Read QUARK Secure SKU Fuse
|
|
return ((QNCAltPortRead (QUARK_SCSS_FUSE_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE) & BIT6) == BIT6);
|
|
}
|