mirror of https://github.com/acidanthera/audk.git
193 lines
3.8 KiB
C
193 lines
3.8 KiB
C
/** @file
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The interface layer for memory controller access.
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It is supporting both real hardware platform and simulation environment.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "mrc.h"
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#include "memory_options.h"
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#include "meminit_utils.h"
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#include "io.h"
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#ifdef SIM
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void SimMmio32Write (
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uint32_t be,
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uint32_t address,
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uint32_t data );
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void SimMmio32Read (
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uint32_t be,
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uint32_t address,
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uint32_t *data );
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void SimDelayClk (
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uint32_t x2clk );
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// This is a simple delay function.
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// It takes "nanoseconds" as a parameter.
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void delay_n(uint32_t nanoseconds)
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{
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SimDelayClk( 800*nanoseconds/1000);
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}
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#endif
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/****
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*
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***/
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uint32_t Rd32(
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uint32_t unit,
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uint32_t addr)
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{
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uint32_t data;
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switch (unit)
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{
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case MEM:
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case MMIO:
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#ifdef SIM
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SimMmio32Read( 1, addr, &data);
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#else
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data = *PTR32(addr);
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#endif
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break;
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case MCU:
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case HOST_BRIDGE:
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case MEMORY_MANAGER:
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case HTE:
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// Handle case addr bigger than 8bit
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pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
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addr &= 0x00FF;
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pciwrite32(0, 0, 0, SB_PACKET_REG,
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SB_COMMAND(SB_REG_READ_OPCODE, unit, addr));
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data = pciread32(0, 0, 0, SB_DATA_REG);
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break;
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case DDRPHY:
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// Handle case addr bigger than 8bit
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pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
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addr &= 0x00FF;
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pciwrite32(0, 0, 0, SB_PACKET_REG,
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SB_COMMAND(SB_DDRIO_REG_READ_OPCODE, unit, addr));
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data = pciread32(0, 0, 0, SB_DATA_REG);
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break;
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default:
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DEAD_LOOP()
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;
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}
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if (unit < MEM)
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DPF(D_REGRD, "RD32 %03X %08X %08X\n", unit, addr, data);
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return data;
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}
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/****
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*
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***/
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void Wr32(
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uint32_t unit,
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uint32_t addr,
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uint32_t data)
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{
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if (unit < MEM)
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DPF(D_REGWR, "WR32 %03X %08X %08X\n", unit, addr, data);
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switch (unit)
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{
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case MEM:
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case MMIO:
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#ifdef SIM
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SimMmio32Write( 1, addr, data);
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#else
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*PTR32(addr) = data;
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#endif
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break;
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case MCU:
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case HOST_BRIDGE:
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case MEMORY_MANAGER:
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case HTE:
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// Handle case addr bigger than 8bit
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pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
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addr &= 0x00FF;
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pciwrite32(0, 0, 0, SB_DATA_REG, data);
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pciwrite32(0, 0, 0, SB_PACKET_REG,
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SB_COMMAND(SB_REG_WRITE_OPCODE, unit, addr));
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break;
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case DDRPHY:
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// Handle case addr bigger than 8bit
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pciwrite32(0, 0, 0, SB_HADR_REG, addr & 0xFFF00);
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addr &= 0x00FF;
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pciwrite32(0, 0, 0, SB_DATA_REG, data);
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pciwrite32(0, 0, 0, SB_PACKET_REG,
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SB_COMMAND(SB_DDRIO_REG_WRITE_OPCODE, unit, addr));
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break;
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case DCMD:
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pciwrite32(0, 0, 0, SB_HADR_REG, 0);
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pciwrite32(0, 0, 0, SB_DATA_REG, data);
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pciwrite32(0, 0, 0, SB_PACKET_REG,
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SB_COMMAND(SB_DRAM_CMND_OPCODE, MCU, 0));
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break;
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default:
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DEAD_LOOP()
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;
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}
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}
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/****
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*
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***/
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void WrMask32(
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uint32_t unit,
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uint32_t addr,
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uint32_t data,
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uint32_t mask)
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{
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Wr32(unit, addr, ((Rd32(unit, addr) & ~mask) | (data & mask)));
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}
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/****
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*
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***/
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void pciwrite32(
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uint32_t bus,
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uint32_t dev,
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uint32_t fn,
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uint32_t reg,
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uint32_t data)
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{
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Wr32(MMIO, PCIADDR(bus,dev,fn,reg), data);
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}
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/****
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*
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***/
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uint32_t pciread32(
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uint32_t bus,
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uint32_t dev,
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uint32_t fn,
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uint32_t reg)
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{
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return Rd32(MMIO, PCIADDR(bus,dev,fn,reg));
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}
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