Hongbin1 Zhang aac5b3eca3 StandaloneMmPkg/MmIpl: Max physical address bits if disable 5 page level ... 4-level paging supports translating 48-bit linear addresses to 52-bit physical addresses. Since linear addresses are sign-extended, the linear-address space of 4-level paging is: [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff]. So only [0, 2^47-1] linear-address range maps to the identical physical-address range when 5-Level paging is disabled. Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>		2024-10-31 13:34:38 +00:00
..
MmCommunicationDxe	StandaloneMmPkg: Create some notification of protocol and Event	2024-08-28 15:25:27 +00:00
StandaloneMmCpu	StandaloneMmPkg: Make StandaloneMmCpu driver architecture independent	2024-02-27 12:27:58 +00:00
StandaloneMmIplPei	StandaloneMmPkg/MmIpl: Max physical address bits if disable 5 page level	2024-10-31 13:34:38 +00:00